Microchip Technology AC244045 Data Sheet
PIC16F72X/PIC16LF72X
DS41341E-page 20
© 2009 Microchip Technology Inc.
FIGURE 2-3:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F726/LF726 AND
PIC16F727/LF727
AND STACK FOR THE
PIC16F726/LF726 AND
PIC16F727/LF727
2.2
Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPRs)
and the Special Function Registers (SFRs). Bits RP0
and RP1 are bank select bits.
which contain the General Purpose Registers (GPRs)
and the Special Function Registers (SFRs). Bits RP0
and RP1 are bank select bits.
RP1
RP0
0
0
→
Bank 0 is selected
0
1
→
Bank 1 is selected
1
0
→
Bank 2 is selected
1
1
→
Bank 3 is selected
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function
Registers are the General Purpose Registers,
implemented as static RAM. All implemented banks
contain Special Function Registers. Some frequently
used Special Function Registers from one bank are
mirrored in another bank for code reduction and
quicker access.
locations of each bank are reserved for the Special
Function Registers. Above the Special Function
Registers are the General Purpose Registers,
implemented as static RAM. All implemented banks
contain Special Function Registers. Some frequently
used Special Function Registers from one bank are
mirrored in another bank for code reduction and
quicker access.
2.2.1
GENERAL PURPOSE REGISTER
FILE
FILE
The register file is organized as 128 x 8 bits in the
PIC16F722/LF722, 192 x 8 bits in the PIC16F723/LF723
and PIC16F724/LF724, and 368 x 8 bits in the
PIC16F726/LF726 and PIC16F727/LF727. Each
register is accessed either directly or indirectly through
the File Select Register (FSR), (Refer to Section 2.5
“Indirect Addressing, INDF and FSR Registers”).
PIC16F722/LF722, 192 x 8 bits in the PIC16F723/LF723
and PIC16F724/LF724, and 368 x 8 bits in the
PIC16F726/LF726 and PIC16F727/LF727. Each
register is accessed either directly or indirectly through
the File Select Register (FSR), (Refer to Section 2.5
“Indirect Addressing, INDF and FSR Registers”).
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (refer to Table 2-1).
These registers are static RAM.
the CPU and peripheral functions for controlling the
desired operation of the device (refer to Table 2-1).
These registers are static RAM.
The Special Function Registers can be classified into
two sets: core and peripheral. The Special Function
Registers associated with the “core” are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.
two sets: core and peripheral. The Special Function
Registers associated with the “core” are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.
PC<12:0>
13
0000h
0004h
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
CALL, RETURN
RETFIE, RETLW
RETFIE, RETLW
Stack Level 2
0005h
On-chip
1FFFh
Program
Memory
Page 0
Page 1
07FFh
0800h
0800h
0FFFh
1000h
1000h
Page 2
Page 3
17FFh
1800h
1800h