Microchip Technology AC244045 Data Sheet
PIC16F72X/PIC16LF72X
DS41341E-page 44
© 2009 Microchip Technology Inc.
4.1
Operation
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
are enabled by setting the following bits:
• GIE bit of the INTCON register
• Interrupt Enable bit(s) for the specific interrupt
event(s)
• PEIE bit of the INTCON register (if the Interrupt
Enable bit of the interrupt event is contained in the
PIE1 and PIE2 registers)
PIE1 and PIE2 registers)
The INTCON, PIR1 and PIR2 registers record individ-
ual interrupts via Interrupt Flag bits. Interrupt Flag bits
will be set, regardless of the status of the GIE, PEIE
and individual Interrupt Enable bits.
ual interrupts via Interrupt Flag bits. Interrupt Flag bits
will be set, regardless of the status of the GIE, PEIE
and individual Interrupt Enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• PC is loaded with the interrupt vector 0004h
The ISR determines the source of the interrupt by
polling the Interrupt Flag bits. The Interrupt Flag bits
must be cleared before exiting the ISR to avoid
polling the Interrupt Flag bits. The Interrupt Flag bits
must be cleared before exiting the ISR to avoid
repeated interrupts. Because the GIE bit is cleared, any
interrupt that occurs while executing the ISR will be
recorded through its Interrupt Flag, but will not cause
the processor to redirect to the interrupt vector.
interrupt that occurs while executing the ISR will be
recorded through its Interrupt Flag, but will not cause
the processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack and setting the GIE bit.
previous address from the stack and setting the GIE bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
operation, refer to its peripheral chapter.
4.2
Interrupt Latency
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is 3 instruction cycles. For asynchronous
interrupts, the latency is 3 to 4 instruction cycles,
depending on when the interrupt occurs. See Figure 4-2
for timing details.
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is 3 instruction cycles. For asynchronous
interrupts, the latency is 3 to 4 instruction cycles,
depending on when the interrupt occurs. See Figure 4-2
for timing details.
FIGURE 4-2:
INT PIN INTERRUPT TIMING
Note 1: Individual Interrupt Flag bits are set,
regardless of the state of any other
enable bits.
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
while the GIE bit is clear will be serviced
when the GIE bit is set again.
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
OSC1
CLKOUT
INT pin
INTF flag
(INTCON<1>)
(INTCON<1>)
GIE bit
(INTCON<7>)
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Fetched
Instruction
Executed
Executed
Interrupt Latency
PC
PC + 1
PC + 1
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (PC)
Inst (PC + 1)
Inst (PC – 1)
Inst (0004h)
Dummy Cycle
Inst (PC)
—
Note 1:
INTF flag is sampled here (every Q1).
2:
Asynchronous interrupt latency = 3-4 T
CY
. Synchronous latency = 3 T
CY
, where T
CY
= instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3:
CLKOUT is available only in INTOSC and RC Oscillator modes.
4:
For minimum width of INT pulse, refer to AC specifications in Section 23.0 “Electrical Specifications”.
5:
INTF is enabled to be set any time during the Q4-Q1 cycles.
(1)
(2)
(3)
(4)
(5)
(1)