Microchip Technology DM163025-1 Data Sheet
2012 Microchip Technology Inc.
DS30684A-page 133
PIC18(L)F2X/45K50
TABLE 10-1:
REGISTERS ASSOCIATED WITH INTERRUPTS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on page
ANSELB
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
IOCIE
TMR0IF
INT0IF
IOCIF
INTCON2
RBPU
INTEDG0 INTEDG1 INTEDG2
—
TMR0IP
—
IOCIP
INTCON3
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF
IOCB
IOCB7
IOCB6
IOCB5
IOCB4
—
—
—
—
IOCC
IOCC7
IOCC6
IOCC5
IOCC4
—
IOCC2
IOCC1
IOCC0
IPR1
ACTIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP
IPR3
—
—
—
—
CTMUIP
USBIP
TMR3GIP TMR1GIP
PIE1
ACTIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
PIE2
OSCFIE
C1IE
C2IE
EEIE
BCLIE
HLVDIE
TMR3IE
CCP2IE
PIE3
—
—
—
—
CTMUIE
USBIE
TMR3GIE TMR1GIE
PIR1
ACTIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF
PIR3
—
—
—
—
CTMUIF
USBIF
TMR3GIF TMR1GIF
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
RCON
IPEN
SBOREN
—
RI
TO
PD
POR
BOR
Legend:
— = unimplemented locations, read as ‘0’. Shaded bits are not used for interrupts.
TABLE 10-2:
CONFIGURATION REGISTERS ASSOCIATED WITH INTERRUPTS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on page
CONFIG3H
MCLRE
SDOMX
—
T3CMX
—
—
PBADEN
CCP2MX
CONFIG4L
DEBUG
XINST
ICPRT
—
—
LVP
—
STRVEN
Legend:
— = unimplemented locations, read as ‘0’. Shaded bits are not used for interrupts.