Microchip Technology DM163025-1 Data Sheet

DS30684A-page 168

 2012 Microchip Technology Inc.

Timer1/3 can be configured to count freely or the count
can be enabled and disabled using Timer1/3 gate
circuitry. This is also referred to as Timer1/3 Gate
Enable.
Timer1/3 gate can also be driven by multiple selectable
sources.

13.7.1

TIMER1/3 GATE ENABLE

The Timer1/3 Gate Enable mode is enabled by setting
the TMRxGE bit of the TxGCON register. The polarity
of the Timer1/3 Gate Enable mode is configured using
the TxGPOL bit of the TxGCON register.
When Timer1/3 Gate Enable mode is enabled,
Timer1/3 will increment on the rising edge of the
Timer1/3 clock source. When Timer1/3 Gate Enable
mode is disabled, no incrementing will occur and
Timer1/3 will hold the current count. See 

for timing details.

13.7.2

TIMER1/3 GATE SOURCE 
SELECTION

The Timer1/3 gate source can be selected from one of
four different sources. Source selection is controlled by
the TxGSS bits of the TxGCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the TxGPOL bit of the
TxGCON register.

13.7.2.1

TxG Pin Gate Operation

The TxG pin is one source for Timer1/3 gate control. It
can be used to supply an external source to the
Timer1/3 gate circuitry.

13.7.2.2

Timer2 Match Gate Operation

The TMR2 register will increment until it matches the
value in the PR2 register. On the very next increment
cycle, TMR2 will be reset to 00h. When this Reset
occurs, a low-to-high pulse will automatically be gener-
ated and internally supplied to the Timer1/3 gate
circuitry. See 

 for more information.

13.7.2.3

Comparator C1 Gate Operation

The output resulting from a Comparator 1 operation can
be selected as a source for Timer1/3 gate control. The
Comparator 1 output (sync_C1OUT) can be
synchronized to the Timer1/3 clock or left asynchronous.
For more information see 

13.7.2.4

Comparator C2 Gate Operation

The output resulting from a Comparator 2 operation
can be selected as a source for Timer1/3 gate control.
The Comparator 2 output (sync_C2OUT) can be
synchronized to the Timer1/3 clock or left
asynchronous. For more information see

.



0

0

Counts



0

1

Holds Count



1

0

Holds Count



1

1

Counts

Internal Data Bus

8

Set 

TMR1IF

on Overflow

TMR1

 High Byte

8

8

8

Read TMR1L

Write TMR1L

8

From 

Timer1/3

Circuitry

00

Timer1/3 Gate Pin (TxG)

01

Timer2 Match to PR2
(TMR2 increments to match PR2)

10

Comparator 1 Output sync_C1OUT
(optionally Timer1/3 synchronized output)

11

Comparator 2 Output sync_C2OUT
(optionally Timer1/3 synchronized output)