Microchip Technology DM163025-1 Data Sheet

DS30684A-page 186

 2012 Microchip Technology Inc.

15.2.4

SPECIAL EVENT TRIGGER

When Special Event Trigger mode is selected
(CCPxM<3:0> = 1011), and a match of the
TMRxH:TMRxL and the CCPRxH:CCPRxL registers
occurs, all CCPx and ECCPx modules will immediately:
• Set the CCP interrupt flag bit – CCPxIF
• CCP2 will start an ADC conversion, if the ADC is 

enabled and TRIGSEL is configured for CCP2.

On the next TimerX rising clock edge:
• A Reset of TimerX register pair occurs – 

TMRxH:TMRxL = 0x0000,

This Special Event Trigger mode does not:
• Assert control over the CCPx or ECCPx pins.
• Set the TMRxIF interrupt bit when the 

TMRxH:TMRxL register pair is reset. (TMRxIF 
gets set on a TimerX overflow.)

If the value of the CCPRxH:CCPRxL registers are
modified when a match occurs, the user should be
aware that the automatic reset of TimerX occurs on the
next rising edge of the clock. Therefore, modifying the
CCPRxH:CCPRxL registers before this reset occurs
will allow the TimerX to continue without being reset,
inadvertently resulting in the next event being
advanced or delayed.
The Special Event Trigger mode allows the
CCPRxH:CCPRxL register pair to effectively provide a
16-bit programmable period register for TimerX.

15.2.5

COMPARE DURING SLEEP

The Compare mode is dependent upon the system
clock (F

OSC

) for proper operation. Since F

OSC

 is shut

down during Sleep mode, the Compare mode will not
function properly during Sleep.