Microchip Technology DM163025-1 Data Sheet
PIC18(L)F2X/45K50
DS30684A-page 234
2012 Microchip Technology Inc.
16.5.3
SLAVE TRANSMISSION
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPxSTAT register is set. The received address is
loaded into the SSPxBUF register, and an ACK pulse is
sent by the slave on the ninth bit.
Following the ACK, slave hardware clears the CKP bit
and the SCL pin is held low (see
and an address match occurs, the R/W bit of the
SSPxSTAT register is set. The received address is
loaded into the SSPxBUF register, and an ACK pulse is
sent by the slave on the ninth bit.
Following the ACK, slave hardware clears the CKP bit
and the SCL pin is held low (see
for more detail). By stretching the
clock, the master will be unable to assert another clock
pulse until the slave is done preparing the transmit
data.
The transmit data must be loaded into the SSPxBUF
register which also loads the SSPxSR register. Then
the SCL pin should be released by setting the CKP bit
of the SSPxCON1 register. The eight data bits are
shifted out on the falling edge of the SCL input. This
ensures that the SDA signal is valid during the SCL
high time.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. This ACK
value is copied to the ACKSTAT bit of the SSPxCON2
register. If ACKSTAT is set (not ACK), then the data
transfer is complete. In this case, when the not ACK is
latched by the slave, the slave goes Idle and waits for
another occurrence of the Start bit. If the SDA line was
low (ACK), the next transmit data must be loaded into
the SSPxBUF register. Again, the SCL pin must be
released by setting bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared by software and
the SSPxSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
pulse until the slave is done preparing the transmit
data.
The transmit data must be loaded into the SSPxBUF
register which also loads the SSPxSR register. Then
the SCL pin should be released by setting the CKP bit
of the SSPxCON1 register. The eight data bits are
shifted out on the falling edge of the SCL input. This
ensures that the SDA signal is valid during the SCL
high time.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. This ACK
value is copied to the ACKSTAT bit of the SSPxCON2
register. If ACKSTAT is set (not ACK), then the data
transfer is complete. In this case, when the not ACK is
latched by the slave, the slave goes Idle and waits for
another occurrence of the Start bit. If the SDA line was
low (ACK), the next transmit data must be loaded into
the SSPxBUF register. Again, the SCL pin must be
released by setting bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared by software and
the SSPxSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
16.5.3.1
Slave Mode Bus Collision
A slave receives a Read request and begins shifting
data out on the SDA line. If a bus collision is detected
and the SBCDE bit of the SSPxCON3 register is set,
the BCLIF bit of the PIRx register is set. Once a bus col-
lision is detected, the slave goes Idle and waits to be
addressed again. User software can use the BCLIF bit
to handle a slave bus collision.
data out on the SDA line. If a bus collision is detected
and the SBCDE bit of the SSPxCON3 register is set,
the BCLIF bit of the PIRx register is set. Once a bus col-
lision is detected, the slave goes Idle and waits to be
addressed again. User software can use the BCLIF bit
to handle a slave bus collision.
16.5.3.2
7-bit Transmission
A master device can transmit a read request to a
slave, and then clock data out of the slave. The list
below outlines what software for a slave will need to do
to accomplish a standard transmission.
slave, and then clock data out of the slave. The list
below outlines what software for a slave will need to do
to accomplish a standard transmission.
can be used as a reference to this list.
1.
1.
Master sends a Start condition on SDA and
SCL.
SCL.
2.
S bit of SSPxSTAT is set; SSPIF is set if interrupt
on Start detect is enabled.
on Start detect is enabled.
3.
Matching address with R/W bit set is received by
the slave setting SSPIF bit.
the slave setting SSPIF bit.
4.
Slave hardware generates an ACK and sets
SSPIF.
SSPIF.
5.
SSPIF bit is cleared by user.
6.
Software reads the received address from
SSPxBUF, clearing BF.
SSPxBUF, clearing BF.
7.
R/W is set so CKP was automatically cleared
after the ACK.
after the ACK.
8.
The slave software loads the transmit data into
SSPxBUF.
SSPxBUF.
9.
CKP bit is set releasing SCL, allowing the mas-
ter to clock the data out of the slave.
ter to clock the data out of the slave.
10. SSPIF is set after the ACK response from the
master is loaded into the ACKSTAT register.
11. SSPIF bit is cleared.
12. The slave software checks the ACKSTAT bit to
12. The slave software checks the ACKSTAT bit to
see if the master wants to clock out more data.
13. Steps 9-13 are repeated for each transmitted
byte.
14. If the master sends a not ACK; the clock is not
held, but SSPIF is still set.
15. The master sends a Restart condition or a Stop.
16. The slave is no longer addressed.
16. The slave is no longer addressed.
Note 1:
If the master ACKs the clock will be
stretched.
stretched.
2:
ACKSTAT is the only bit updated on the
rising edge of SCL (9th) rather than the
falling.
rising edge of SCL (9th) rather than the
falling.