Microchip Technology DM163025-1 Data Sheet
PIC18(L)F2X/45K50
DS30684A-page 254
2012 Microchip Technology Inc.
16.6.13
MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
BUS COLLISION AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus
arbitration. When the master outputs address/data bits
onto the SDA pin, arbitration takes place when the
master outputs a ‘1’ on SDA, by letting SDA float high
and another master asserts a ‘0’. When the SCL pin
floats high, data should be stable. If the expected data
on SDA is a ‘1’ and the data sampled on the SDA pin is
‘0’, then a bus collision has taken place. The master will
set the Bus Collision Interrupt Flag, BCLIF, and reset
the I
arbitration. When the master outputs address/data bits
onto the SDA pin, arbitration takes place when the
master outputs a ‘1’ on SDA, by letting SDA float high
and another master asserts a ‘0’. When the SCL pin
floats high, data should be stable. If the expected data
on SDA is a ‘1’ and the data sampled on the SDA pin is
‘0’, then a bus collision has taken place. The master will
set the Bus Collision Interrupt Flag, BCLIF, and reset
the I
2
C port to its Idle state (
).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPxBUF can be written to. When the user services
the bus collision Interrupt Service Routine and if the I
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPxBUF can be written to. When the user services
the bus collision Interrupt Service Routine and if the I
2
C
bus is free, the user can resume communication by
asserting a Start condition.
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are deasserted and the respective control bits in
the SSPxCON2 register are cleared. When the user
services the bus collision Interrupt Service Routine and
if the I
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are deasserted and the respective control bits in
the SSPxCON2 register are cleared. When the user
services the bus collision Interrupt Service Routine and
if the I
2
C bus is free, the user can resume
communication by asserting a Start condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPxBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPxBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I
2
C
bus can be taken when the P bit is set in the SSPxSTAT
register, or the bus is Idle and the S and P bits are
cleared.
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 16-32:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDA
SCL
BCLIF
SDA released
SDA line pulled low
by another source
Sample SDA. While SCL is high,
data does not match what is driven
data does not match what is driven
Bus collision has occurred.
Set bus collision
interrupt (BCLIF)
interrupt (BCLIF)
by the master.
by master
Data changes
while SCL = 0
while SCL = 0