Microchip Technology DM163025-1 Data Sheet
PIC18(L)F2X/45K50
DS30684A-page 336
2012 Microchip Technology Inc.
REGISTER 20-2:
CTMUCONL: CTMU CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EDG2POL
EDG2SEL<1:0>
EDG1POL
EDG1SEL<1:0>
EDG2STAT
EDG1STAT
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EDG2POL:
Edge 2 Polarity Select bit
1
= Edge 2 programmed for a positive edge response
0
= Edge 2 programmed for a negative edge response
bit 6-5
EDG2SEL<1:0>:
Edge 2 Source Select bits
11
= CTED1 pin
10
= CTED2 pin
01
= ECCP1 Special Event Trigger
00
= CCP2 Special Event Trigger
bit 4
EDG1POL:
Edge 1 Polarity Select bit
1
= Edge 1 programmed for a positive edge response
0
= Edge 1 programmed for a negative edge response
bit 3-2
EDG1SEL<1:0>:
Edge 1 Source Select bits
11
= CTED1 pin
10
= CTED2 pin
01
= ECCP1 Special Event Trigger
00
= CCP2 Special Event Trigger
bit 1
EDG2STAT:
Edge 2 Status bit
1
= Edge 2 event has occurred
0
= Edge 2 event has not occurred
bit 0
EDG1STAT:
Edge 1 Status bit
1
= Edge 1 event has occurred
0
= Edge 1 event has not occurred