Microchip Technology DM163025-1 Data Sheet
2012 Microchip Technology Inc.
DS30684A-page 359
PIC18(L)F2X/45K50
24.2.5
USB ADDRESS REGISTER
(UADDR)
(UADDR)
The USB Address register contains the unique USB
address that the peripheral will decode when active.
UADDR is reset to 00h when a USB Reset is received,
indicated by URSTIF, or when a Reset is received from
the microcontroller. The USB address must be written
by the microcontroller during the USB setup phase
(enumeration) as part of the Microchip USB firmware
support.
address that the peripheral will decode when active.
UADDR is reset to 00h when a USB Reset is received,
indicated by URSTIF, or when a Reset is received from
the microcontroller. The USB address must be written
by the microcontroller during the USB setup phase
(enumeration) as part of the Microchip USB firmware
support.
24.2.6
USB FRAME NUMBER REGISTERS
(UFRMH:UFRML)
(UFRMH:UFRML)
The Frame Number registers contain the 11-bit frame
number. The low-order byte is contained in UFRML,
while the three high-order bits are contained in
UFRMH. The register pair is updated with the current
frame number whenever a SOF token is received. For
the microcontroller, these registers are read-only. The
Frame Number registers are primarily used for
isochronous transfers. The contents of the UFRMH and
UFRML registers are only valid when the 48 MHz SIE
clock is active (i.e., contents are inaccurate when
SUSPND (UCON<1>) bit = 1).
number. The low-order byte is contained in UFRML,
while the three high-order bits are contained in
UFRMH. The register pair is updated with the current
frame number whenever a SOF token is received. For
the microcontroller, these registers are read-only. The
Frame Number registers are primarily used for
isochronous transfers. The contents of the UFRMH and
UFRML registers are only valid when the 48 MHz SIE
clock is active (i.e., contents are inaccurate when
SUSPND (UCON<1>) bit = 1).
24.3
USB RAM
USB data moves between the microcontroller core and
the SIE through a memory space known as the USB
RAM. This is a special dual access memory that is
mapped into the normal data memory space in Banks
4 through 7 (400h to 7FFh) for a total of 1024 bytes
(
the SIE through a memory space known as the USB
RAM. This is a special dual access memory that is
mapped into the normal data memory space in Banks
4 through 7 (400h to 7FFh) for a total of 1024 bytes
(
).
Bank 4 (400h through 4FFh) is used specifically for
endpoint buffer control. Depending on the type of
buffering being used, all but eight bytes of Bank 4 may
also be available for use as USB buffer space.
Although USB RAM is available to the microcontroller
as data memory, the sections that are being accessed
by the SIE should not be accessed by the
microcontroller. A semaphore mechanism is used to
determine the access to a particular buffer at any given
time. This is discussed in
endpoint buffer control. Depending on the type of
buffering being used, all but eight bytes of Bank 4 may
also be available for use as USB buffer space.
Although USB RAM is available to the microcontroller
as data memory, the sections that are being accessed
by the SIE should not be accessed by the
microcontroller. A semaphore mechanism is used to
determine the access to a particular buffer at any given
time. This is discussed in
.
FIGURE 24-4:
IMPLEMENTATION OF
USB RAM IN DATA
MEMORY SPACE
USB RAM IN DATA
MEMORY SPACE
400h
7FFh
Buffer Descriptors,
USB Data or User Data
SFRs
3FFh
000h
F60h
FFFh
Banks 4 to 7
(USB RAM)
(USB RAM)
F5Fh
F53h
F52h
800h
Banks 8
to 14
User Data
Unused
Banks 15
USB Data or
User Data
4FFh
500h
500h