Microchip Technology DM163025-1 Data Sheet

DS30684A-page 398

 2012 Microchip Technology Inc.

For PIC18(L)F2X/45K50 devices, the WDT is driven by
the INTRC source. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the INTRC
oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in Configu-
ration Register 2H. Available periods range from 4 ms
to 131.072 seconds (2.18 minutes). The WDT and
postscaler are cleared when any of the following events
occur: a SLEEP or CLRWDT instruction is executed, the
IRCF bits of the OSCCON register are changed or a
clock failure has occurred.

The  CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.

Changing the setting of the IRCF bits of
the OSCCON register clears the WDT
and postscaler counts.

When a CLRWDT instruction is executed,
the postscaler count will be cleared.

INTRC Source

WDT 

Wake-up

Reset

 WDT Counter

Programmable Postscaler

1:1 to 1:32,768

Enable WDT

WDTPS<3:0>

SWDTEN

WDTEN

CLRWDT

4

from Power

Reset

All Device Resets

Sleep

128

Change on IRCF bits

Managed Modes