Microchip Technology DM163025-1 Data Sheet

DS30684A-page 44

 2012 Microchip Technology Inc.

The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS<1:0>) bits of the
OSCCON register.
PIC18(L)F2X/45K50 devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs
during the clock switch. The length of this pause is the
sum of two cycles of the old clock source and three to
four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Clock transitions are discussed in greater detail in

3.11.1

SYSTEM CLOCK SELECT 
(SCS<1:0>) BITS

The System Clock Select (SCS<1:0>) bits of the
OSCCON register select the system clock source that
is used for the CPU and peripherals.
• When SCS<1:0> = 00, the system clock source is 

determined by configuration of the FOSC<3:0> 
bits in the CONFIG1H Configuration register.

• When SCS<1:0> = 10, the system clock source is 

chosen by the internal oscillator frequency 
selected by the INTSRC bit of the OSCCON2<5> 
register and the IRCF<2:0> bits of the OSCCON 
register. 

• When SCS<1:0> = 01, the system clock source is 

the 32.768 kHz secondary oscillator shared with 
Timer1 and Timer3.

After a Reset, the SCS<1:0> bits of the OSCCON
register are always cleared.

3.11.2

OSCILLATOR START-UP TIME-OUT 
STATUS (OSTS) BIT

The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCCON register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<3:0> bits in the CONFIG1H
Configuration register, or from the internal clock
source. In particular, when the primary oscillator is the
source of the primary clock, OSTS indicates that the
Oscillator Start-up Timer (OST) has timed out for LP,
XT or HS modes.

3.11.3

CLOCK SWITCH TIMING

When switching between one oscillator and another,
the new oscillator may not be operating which saves
power (see 

). If this is the case, there is a

delay after the SCS<1:0> bits of the OSCCON register
are modified before the frequency change takes place.
The OSTS and HFIOFR, LFIOFS bits of the OSCCON
and OSCCON2 registers will reflect the current active
status of the external and HFINTOSC oscillators. The
timing of a frequency selection is as follows:
1.

SCS<1:0> bits of the OSCCON register are
modified.

2.

The old clock continues to operate until the new
clock is ready.

3.

Clock switch circuitry waits for two consecutive
rising edges of the old clock after the new clock
ready signal goes true.

4.

The system clock is held low starting at the next
falling edge of the old clock.

5.

Clock switch circuitry waits for an additional two
rising edges of the new clock.

6.

On the next falling edge of the new clock the low
hold on the system clock is released and new
clock is switched in as the system clock.

7.

Clock switch is complete.

See 

 for more details.

If the HFINTOSC is the source of both the old and new
frequency, there is no start-up delay before the new
frequency is active. This is because the old and new
frequencies are derived from the HFINTOSC via the
postscaler and multiplexer.
Start-up delay specifications are located in

, under AC

Specifications (Oscillator Module).

Any automatic clock switch, which may
occur from Two-Speed Start-up or Fail-
Safe Clock Monitor, does not update the
SCS<1:0> bits of the OSCCON register.
The user can monitor the SOSCRUN and
LFIOFS bits of the OSCCON2 register, and
the HFIOFS and OSTS bits of the
OSCCON register to determine the current
system clock source.