Microchip Technology DM163025-1 Data Sheet
PIC18(L)F2X/45K50
DS30684A-page 488
2012 Microchip Technology Inc.
FIGURE 29-12:
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
TABLE 29-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0 OR 1)
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
73
TdiV2scH,
TdiV2scL
TdiV2scL
Setup Time of SDI Data Input to SCK Edge
25
—
ns
74
TscH2diL,
TscL2diL
TscL2diL
Hold Time of SDI Data Input to SCK Edge
25
—
ns
75
TdoR
SDO Data Output Rise Time
—
30
ns
76
TdoF
SDO Data Output Fall Time
—
20
ns
78
TscR
SCK Output Rise Time
(Master mode)
(Master mode)
—
30
ns
79
TscF
SCK Output Fall Time (Master mode)
—
20
ns
80
TscH2doV,
TscL2doV
TscL2doV
SDO Data Output Valid after SCK Edge
—
20
ns
81
TdoV2scH,
TdoV2scL
TdoV2scL
SDO Data Output Setup to SCK Edge
T
CY
—
ns
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71
72
74
75, 76
78
80
MSb
79
73
MSb In
bit 6 - - - - - -1
LSb In
bit 6 - - - -1
LSb
Note:
for load conditions.