Microchip Technology DM163025-1 Data Sheet
2012 Microchip Technology Inc.
DS30684A-page 493
PIC18(L)F2X/45K50
FIGURE 29-17:
MASTER SSP I
2
C™ BUS START/STOP BITS TIMING WAVEFORMS
FIGURE 29-18:
MASTER SSP I
2
C™ BUS DATA TIMING
Note:
Refer to
91
93
SCL
SDA
Start
Condition
Stop
Condition
90
92
TABLE 29-18: MASTER SSP I
2
C™ BUS START/STOP BITS REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max
Units
Conditions
90
T
SU
:
STA
Start Condition
100 kHz mode
2(T
OSC
)(BRG + 1)
—
ns
Only relevant for
Repeated Start
condition
Repeated Start
condition
Setup Time
400 kHz mode
2(T
OSC
)(BRG + 1)
—
1 MHz mode
(1)
2(T
OSC
)(BRG + 1)
—
91
T
HD
:
STA
Start Condition
100 kHz mode
2(T
OSC
)(BRG + 1)
—
ns
After this period, the
first clock pulse is
generated
first clock pulse is
generated
Hold Time
400 kHz mode
2(T
OSC
)(BRG + 1)
—
1 MHz mode
(1)
2(T
OSC
)(BRG + 1)
—
92
T
SU
:
STO
Stop Condition
100 kHz mode
2(T
OSC
)(BRG + 1)
—
ns
Setup Time
400 kHz mode
2(T
OSC
)(BRG + 1)
—
1 MHz mode
(1)
2(T
OSC
)(BRG + 1)
—
93
T
HD
:
STO
Stop Condition
100 kHz mode
2(T
OSC
)(BRG + 1)
—
ns
Hold Time
400 kHz mode
2(T
OSC
)(BRG + 1)
—
1 MHz mode
(1)
2(T
OSC
)(BRG + 1)
—
Note 1:
Maximum pin capacitance = 10 pF for all I
2
C pins.
Note:
Refer to
for load conditions.
90
91
92
100
101
103
106
107
109
109
110
102
SCL
SDA
In
SDA
Out