Microchip Technology DM163025-1 Data Sheet
2012 Microchip Technology Inc.
DS30684A-page 59
PIC18(L)F2X/45K50
4.3
Sleep Mode
The Power-Managed Sleep mode in the PIC18(L)F2X/
45K50 devices is identical to the legacy Sleep mode
offered in all other PIC
45K50 devices is identical to the legacy Sleep mode
offered in all other PIC
®
microcontroller devices. It is
entered by clearing the IDLEN bit of the OSCCON
register and executing the SLEEP instruction. This shuts
down the selected oscillator (
register and executing the SLEEP instruction. This shuts
down the selected oscillator (
) and all clock
source status bits are cleared.
Entering the Sleep mode from either Run or Idle mode
does not require a clock switch. This is because no
clocks are needed once the controller has entered
Sleep. If the WDT is selected, the INTRC source will
continue to operate. If the SOSC oscillator is enabled,
it will also continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS<1:0> bits
becomes ready (see
Entering the Sleep mode from either Run or Idle mode
does not require a clock switch. This is because no
clocks are needed once the controller has entered
Sleep. If the WDT is selected, the INTRC source will
continue to operate. If the SOSC oscillator is enabled,
it will also continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS<1:0> bits
becomes ready (see
), or it will be clocked
from the internal oscillator block if either the Two-Speed
Start-up or the Fail-Safe Clock Monitor are enabled
(see
(see
). In
either case, the OSTS bit is set when the primary clock
is providing the device clocks. The IDLEN and SCS bits
are not affected by the wake-up.
is providing the device clocks. The IDLEN and SCS bits
are not affected by the wake-up.
4.3.1
VOLTAGE REGULATOR POWER
MODE
MODE
On F devices, an internal voltage regulator provides
power to the internal core logic of the chip. During
Sleep mode, the internal voltage regulator can be put
into a lower-power mode, in exchange for longer
wake-up time. Similarly, the internal band gap voltage
reference may be turned off during Sleep for lower-
power consumption. See
power to the internal core logic of the chip. During
Sleep mode, the internal voltage regulator can be put
into a lower-power mode, in exchange for longer
wake-up time. Similarly, the internal band gap voltage
reference may be turned off during Sleep for lower-
power consumption. See
On LF devices, the internal core logic operates from
V
V
DD
and the internal voltage regulator is bypassed. The
VREGCON register is, thus, not implemented on LF
devices.
devices.
REGISTER 4-1:
VREGCON – VOLTAGE REGULATOR POWER CONTROL REGISTER
(1)
U-0
U-0
U-0
U-0
U-0
R-0
R/W-0/0
R/W-0/0
—
—
—
—
—
—
VREGPM<1:0>
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other resets ‘0’ = Bit is cleared ‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
bit 7-2
Unimplemented:
Read as ‘0’
bit 1-0
VREGPM<1:0>:
Voltage Regulator Power mode bits
11
= Band gap not forced in Sleep; LDO off in Sleep; ULP Regulator active
10
= Band gap forced in Sleep; LDO off in Sleep; ULP Regulator active
01
= LDO in Low-Power mode in Sleep, if no peripherals require High-Power mode.
00
= LDO in High-Power mode – always
Note 1:
Reset state depends on state of the IESO Configuration bit.
2:
Default output frequency of HFINTOSC on Reset.