Microchip Technology DM330023-2 Data Sheet
© 2007-2012 Microchip Technology Inc.
DS70283K-page 167
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
REGISTER 15-6:
PWM
x
CON2: PWM CONTROL REGISTER 2
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
SEVOPS<3:0>
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
IUE
OSYNC
UDIS
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
Unimplemented: Read as ‘0’
bit 11-8
SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits
1111 = 1:16 postscale
•
•
•
0001 = 1:2 postscale
0000 = 1:1 postscale
1111 = 1:16 postscale
•
•
•
0001 = 1:2 postscale
0000 = 1:1 postscale
bit 7-3
Unimplemented: Read as ‘0’
bit 2
IUE: Immediate Update Enable bit
1 = Updates to the active PxDC registers are immediate
0 = Updates to the active PxDC registers are synchronized to the PWM time base
1 = Updates to the active PxDC registers are immediate
0 = Updates to the active PxDC registers are synchronized to the PWM time base
bit 1
OSYNC: Output Override Synchronization bit
1 = Output overrides via the PxOVDCON register are synchronized to the PWM time base
0 = Output overrides via the PxOVDCON register occur on next T
1 = Output overrides via the PxOVDCON register are synchronized to the PWM time base
0 = Output overrides via the PxOVDCON register occur on next T
CY
boundary
bit 0
UDIS: PWM Update Disable bit
1 = Updates from Duty Cycle and Period Buffer registers are disabled
0 = Updates from Duty Cycle and Period Buffer registers are enabled
1 = Updates from Duty Cycle and Period Buffer registers are disabled
0 = Updates from Duty Cycle and Period Buffer registers are enabled