Microchip Technology DM330023-2 Data Sheet
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
DS70283K-page 202
© 2007-2012 Microchip Technology Inc.
FIGURE 20-3:
ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM
20.3
ADC Helpful Tips
1.
The SMPI<3:0> (AD1CON2<5:2>) control bits:
a) Determine when the ADC interrupt flag is
a) Determine when the ADC interrupt flag is
set and an interrupt is generated if enabled.
b) When the CSCNA bit (AD1CON2<10>) is
set to ‘1’, determines when the ADC analog
scan channel list defined in the
AD1CSSL/AD1CSSH registers starts over
from the beginning.
scan channel list defined in the
AD1CSSL/AD1CSSH registers starts over
from the beginning.
c)
On devices without a DMA peripheral,
determines when ADC result buffer pointer
to ADC1BUF0-ADC1BUFF, gets reset back
to the beginning at ADC1BUF0.
determines when ADC result buffer pointer
to ADC1BUF0-ADC1BUFF, gets reset back
to the beginning at ADC1BUF0.
2.
On devices without a DMA module, the ADC has
16 result buffers. ADC conversion results are
stored sequentially in ADC1BUF0-ADC1BUFF
regardless of which analog inputs are being
used subject to the SMPI<3:0> bits
(AD1CON2<5:2>) and the condition described
in 1c above. There is no relationship between
the ANx input being measured and which ADC
buffer (ADC1BUF0-ADC1BUFF) that the
conversion results will be placed in.
16 result buffers. ADC conversion results are
stored sequentially in ADC1BUF0-ADC1BUFF
regardless of which analog inputs are being
used subject to the SMPI<3:0> bits
(AD1CON2<5:2>) and the condition described
in 1c above. There is no relationship between
the ANx input being measured and which ADC
buffer (ADC1BUF0-ADC1BUFF) that the
conversion results will be placed in.
3.
On devices with a DMA module, the ADC mod-
ule has only 1 ADC result buffer, (i.e.,
ADC1BUF0), per ADC peripheral and the ADC
conversion result must be read either by the
CPU or DMA controller before the next ADC
conversion is complete to avoid overwriting the
previous value.
ule has only 1 ADC result buffer, (i.e.,
ADC1BUF0), per ADC peripheral and the ADC
conversion result must be read either by the
CPU or DMA controller before the next ADC
conversion is complete to avoid overwriting the
previous value.
4.
The DONE bit (AD1CON1<0>) is only cleared at
the start of each conversion and is set at the
completion of the conversion, but remains set
indefinitely even through the next sample phase
until the next conversion begins. If application
code is monitoring the DONE bit in any kind of
software loop, the user must consider this
the start of each conversion and is set at the
completion of the conversion, but remains set
indefinitely even through the next sample phase
until the next conversion begins. If application
code is monitoring the DONE bit in any kind of
software loop, the user must consider this
behavior because the CPU code execution is
faster than the ADC. As a result, in manual sam-
ple mode, particularly where the users code is
setting the SAMP bit (AD1CON1<1>), the
DONE bit should also be cleared by the user
application just before setting the SAMP bit.
faster than the ADC. As a result, in manual sam-
ple mode, particularly where the users code is
setting the SAMP bit (AD1CON1<1>), the
DONE bit should also be cleared by the user
application just before setting the SAMP bit.
5.
On devices with two ADC modules, the
ADCxPCFG registers for both ADC modules
must be set to a logic ‘1’ to configure a target
I/O pin as a digital I/O pin. Failure to do so
means that any alternate digital input function
will always see only a logic ‘0’ as the digital
input buffer is held in Disable mode.
ADCxPCFG registers for both ADC modules
must be set to a logic ‘1’ to configure a target
I/O pin as a digital I/O pin. Failure to do so
means that any alternate digital input function
will always see only a logic ‘0’ as the digital
input buffer is held in Disable mode.
20.4
ADC Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this
, contains the latest updates
and additional information.
20.4.1
KEY RESOURCES
• Section 16. “Analog-to-Digital Converter
(ADC)” (DS70183)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related dsPIC33F/PIC24H Family Reference
• Application Notes
• Software Libraries
• Webinars
• All related dsPIC33F/PIC24H Family Reference
Manuals Sections
• Development Tools
0
1
ADC Internal
RC Clock
RC Clock
(2)
T
OSC(1)
X
2
ADC Conversion
Clock Multiplier
Clock Multiplier
1, 2, 3, 4, 5,..., 64
AD1CON3<15>
T
CY
T
AD
6
AD1CON3<5:0>
Note 1: Refer to
for the derivation of F
OSC
when the PLL is enabled. If the PLL is not used, F
OSC
is equal
to the clock frequency. T
OSC
= 1/F
OSC
.
2: See the ADC Electrical Characteristics for the exact RC clock value.
Note:
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