Microchip Technology DM330023-2 Data Sheet

Microchip Technology

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

DS70283K-

page 38

©

2007-

2012 Microchip T

echnolo

gy Inc.

TABLE 4-8:

6-OUTPUT PWM1 REGISTER MAP

SFR Name

Addr.

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset State

P1TCON

01C0

PTEN

—

PTSIDL

—

—

—

—

—

PTOPS<3:0>

PTCKPS<1:0>

PTMOD<1:0>

0000 0000 0000 0000

P1TMR

01C2

PTDIR

PWM Timer Count Value Register

0000 0000 0000 0000

P1TPER

01C4

—

PWM Time Base Period Register

0000 0000 0000 0000

P1SECMP

01C6 SEVTDIR

PWM Special Event Compare Register

0000 0000 0000 0000

PWM1CON1 01C8

—

—

—

—

—

PMOD3

PMOD2

PMOD1

—

PEN3H

PEN2H

PEN1H

—

PEN3L

PEN2L

PEN1L

0000 0000 1111 1111

PWM1CON2 01CA

—

—

—

—

SEVOPS<3:0>

—

—

—

—

—

IUE

OSYNC

UDIS

0000 0000 0000 0000

P1DTCON1

01CC

DTBPS<1:0>

DTB<5:0>

DTAPS<1:0>

DTA<5:0>

0000 0000 0000 0000

P1DTCON2

01CE

—

—

—

—

—

—

—

—

—

—

DTS3A

DTS3I

DTS2A

DTS2I

DTS1A

DTS1I

0000 0000 0000 0000

P1FLTACON 01D0

—

—

FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L

FLTAM

—

—

—

—

FAEN3

FAEN2

FAEN1

0000 0000 0000 0000

P1OVDCON 01D4

—

—

POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L

—

—

POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L

1111 1111 0000 0000

P1DC1

01D6

PWM Duty Cycle #1 Register

0000 0000 0000 0000

P1DC2

01D8

PWM Duty Cycle #2 Register

0000 0000 0000 0000

P1DC3

01DA

PWM Duty Cycle #3 Register

0000 0000 0000 0000

Legend:

u = uninitialized bit, — = unimplemented, read as ‘0’

TABLE 4-9:

2-OUTPUT PWM2 REGISTER MAP

SFR Name

Addr.

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset State

P2TCON

05C0

PTEN

—

PTSIDL

—

—

—

—

—

PTOPS<3:0>

PTCKPS<1:0>

PTMOD<1:0>

0000 0000 0000 0000

P2TMR

05C2

PTDIR

PWM Timer Count Value Register

0000 0000 0000 0000

P2TPER

05C4

—

PWM Time Base Period Register

0000 0000 0000 0000

P2SECMP

05C6 SEVTDIR

PWM Special Event Compare Register

0000 0000 0000 0000

PWM2CON1 05C8

—

—

—

—

—

—

—

PMOD1

—

—

—

PEN1H

—

—

—

PEN1L 0000 0000 1111 1111

PWM2CON2 05CA

—

—

—

—

SEVOPS<3:0>

—

—

—

—

—

IUE

OSYNC

UDIS

0000 0000 0000 0000

P2DTCON1

05CC

DTBPS<1:0>

DTB<5:0>

DTAPS<1:0>

DTA<5:0>

0000 0000 0000 0000

P2DTCON2

05CE

—

—

—

—

—

—

—

—

—

—

—

—

—

—

DTS1A

DTS1I

0000 0000 0000 0000

P2FLTACON 05D0

—

—

—

—

—

—

FAOV1H FAOV1L FLTAM

—

—

—

—

—

—

FAEN1 0000 0000 0000 0000

P2OVDCON

05D4

—

—

—

—

—

—

POVD1H POVD1L

—

—

—

—

—

—

POUT1H POUT1L 1111 1111 0000 0000

P2DC1

05D6

PWM Duty Cycle #1 Register

0000 0000 0000 0000

Legend:

u = uninitialized bit, — = unimplemented, read as ‘0’