Microchip Technology DM330023-2 Data Sheet
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
DS70283K-page 56
© 2007-2012 Microchip Technology Inc.
5.2
RTSP Operation
The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
Flash program memory array is organized into rows of 64
instructions or 192 bytes. RTSP allows the user
application to erase a page of memory, which consists of
eight rows (512 instructions) at a time, and to program
one row or one word at a time.
Flash program memory array is organized into rows of 64
instructions or 192 bytes. RTSP allows the user
application to erase a page of memory, which consists of
eight rows (512 instructions) at a time, and to program
one row or one word at a time.
shows typical
erase and programming times. The 8-row erase pages
and single row write rows are edge-aligned from the
beginning of program memory, on boundaries of 1536
bytes and 192 bytes, respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers sequentially. The
instruction words loaded must always be from a group
of 64 boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
All of the table write operations are single-word writes
(two instruction cycles) because only the buffers are
written. A programming cycle is required for
programming each row.
and single row write rows are edge-aligned from the
beginning of program memory, on boundaries of 1536
bytes and 192 bytes, respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers sequentially. The
instruction words loaded must always be from a group
of 64 boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
All of the table write operations are single-word writes
(two instruction cycles) because only the buffers are
written. A programming cycle is required for
programming each row.
5.3
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the
programming operation is finished.
The programming time depends on the FRC accuracy
(see
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the
programming operation is finished.
The programming time depends on the FRC accuracy
(see
, “
”) and the value of the FRC Oscillator Tuning
register (see
). Use the following formula to
calculate the minimum and maximum values for the
Row Write Time, Page Erase Time, and Word Write
Cycle Time parameters (see
Row Write Time, Page Erase Time, and Word Write
Cycle Time parameters (see
”).
EQUATION 5-1:
PROGRAMMING TIME
For example, if the device is operating at +125
° C, the
FRC accuracy will be ±5%. If the TUN<5:0> bits (see
) are set to ‘b111111,the minimum row
write time is equal to
.
EQUATION 5-2:
MINIMUM ROW WRITE
TIME
TIME
The maximum row write time is equal to
EQUATION 5-3:
MAXIMUM ROW WRITE
TIME
TIME
Setting the WR bit (NVMCON<15>) starts the opera-
tion, and the WR bit is automatically cleared when the
operation is finished.
tion, and the WR bit is automatically cleared when the
operation is finished.
5.4
Flash Memory Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this
, contains the latest updates
and additional information.
5.4.1
KEY RESOURCES
• Section 5. “Flash Programming” (DS70191)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related dsPIC33F/PIC24H Family Reference
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related dsPIC33F/PIC24H Family Reference
Manuals Sections
• Development Tools
5.5
Control Registers
Two SFRs are used to read and write the program
Flash memory: NVMCON and NVMKEY.
The NVMCON register (
Flash memory: NVMCON and NVMKEY.
The NVMCON register (
) controls which
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user application must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to
programmed and the start of the programming cycle.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user application must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to
for further details.
T
7.37 MHz
FRC Accuracy
(
)%
FRC Tuning
(
)%
×
×
----------------------------------------------------------------------------------------------------------------------------
Note:
In the event you are not able to access
the product page using the link above,
enter this URL in your browser:
the product page using the link above,
enter this URL in your browser:
T
RW
11064 Cycles
7.37 MHz
1 0.05
+
(
)
1 0.00375
–
(
)
×
×
------------------------------------------------------------------------------------------------ 1.435ms
=
=
T
RW
11064 Cycles
7.37 MHz
1 0.05
–
(
)
1 0.00375
–
(
)
×
×
------------------------------------------------------------------------------------------------ 1.586ms
=
=