Microchip Technology TDGL002 - chipKIT Uno32 Development Board TDGL002 TDGL002 Data Sheet

Product codes
TDGL002
Page of 214
PIC32MX3XX/4XX
DS61143H-page 186
© 2011 Microchip Technology Inc.
FIGURE 29-21:
PARALLEL MASTER PORT READ TIMING DIAGRAM 
  
T
PB
T
PB
T
PB
T
PB
T
PB
T
PB
T
PB
T
PB
PB Clock
PMALL/PMALH
PMD<7:0>
PMA<13:18>
PMRD
PMCS<2:1>
PMWR
PM5
Data
Address<7:0>
PM1
PM3
PM6
Data
PM7
Address<7:0>
Address
PM4
PM2
TABLE 29-38: PARALLEL MASTER PORT READ TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature
-40°C 
≤ T
A
 
≤ +85°C for Industrial
-40°C 
≤ T
A
 
≤ +105°C for V-Temp
Param. 
No.
Symbol
Characteristics
(1)
Min.
Typical
Max.
Units
Conditions
PM1
T
LAT
PMALL/PMALH Pulse Width
1 T
PB
PM2
T
ADSU
Address Out Valid to PMALL/PMALH 
Invalid (address setup time)
2  T
PB
PM3
T
ADHOLD
PMALL/PMALH Invalid to Address 
Out Invalid (address hold time)
1  T
PB
PM4
T
AHOLD
PMRD Inactive to Address Out 
Invalid
(address hold time)
5
ns
PM5
T
RD
PMRD Pulse Width
1 T
PB
PM6
T
DSU
PMRD or PMENB Active to Data In 
Valid (data setup time)
15
ns
PM7
T
DHOLD
PMRD or PMENB Inactive to Data In 
Invalid (data hold time)
80
ns
Note 1:
These parameters are characterized, but not tested in manufacturing.