Microchip Technology TDGL002 - chipKIT Uno32 Development Board TDGL002 TDGL002 Data Sheet

Product codes

TDGL002

PIC32MX3XX/4XX

DS61143H

-page 50

2011 Microchip T

chnolo

y Inc.

TABLE 4-1:

BUS MATRIX REGISTERS MAP

irtual Address

(BF88_#

)

Regis

ter

Bit Range

Bits

All

Res

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

2000

BMX

CON

(1)

31:16

—

BMXCHEDMA

—

BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F

15:0

—

BMXWSDRM

—

BMXARB<2:0>

0042

2010

BMX

DKPBA

(1)

31:16

—

0000

15:0

BMXDKPBA<15:0>

0000

2020

BMX

DUDBA

(1)

31:16

—

0000

15:0

BMXDUDBA<15:0>

0000

2030

BMX

DUPBA

(1)

31:16

—

0000

15:0

BMXDUPBA<15:0>

0000

2040

BMX

DRMSZ

31:16

BMXDRMSZ<31:0>

xxxx

15:0

xxxx

2050

BMX

PUPBA

(1)

31:16

—

BMXPUPBA<19:16>

0000

15:0

BMXPUPBA<15:0>

0000

2060

BMX

PFMSZ

31:16

BMXPFMSZ<31:0>

xxxx

15:0

xxxx

2070

BMX

BOOTSZ

31:16

BMXBOOTSZ<31:0>

0000

15:0

3000

Legend:

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See

Section 12.1.1 “CLR, SET and INV Registers”

for more information.