Microchip Technology ADM00419 Data Sheet

Page of 82
MCP2210
DS22288A-page 10
 2011 Microchip Technology Inc.
• The delay between subsequent data bytes 
(
FIGURE 2-2:
DATA-TO-DATA DELAY
• The delay between the end of the last byte (of the 
SPI transfer) and the de-assertion of the Chip 
Select(s)
FIGURE 2-3:
DATA TO CHIP SELECT 
DELAY
For a particular SPI transfer, the user can choose any
number (out of the available ones) of Chip Select pins.
The SPI transfer parameters contain two fields where
the user will specify the Chip Select values when the
SPI transfer is active/idle. This mechanism allows the
user to specify any combination of Chip Select values
for the Idle mode and some other combination for the
Active mode (SPI transfer active).
T
DATA2DATA
CS
SCK
MOSI
MISO
T
DATA2CS
CS
SCK
MOSI
MISO