Microchip Technology ADM00419 Data Sheet
MCP2210
DS22288A-page 6
2011 Microchip Technology Inc.
In order to meet the inrush current requirements of the
USB 2.0 specifications, the total effective capacitance
appearing across V
USB 2.0 specifications, the total effective capacitance
appearing across V
BUS
and ground must be no more
than 10 µF.
If it is more than 10 µF, some kind of inrush
limiting is required. For more details on Inrush Current
Limiting, see the current Universal Serial Bus Specifi-
cation.
According to the USB 2.0 specification, all USB devices
must also support a Low-Power Suspend mode. In the
USB Suspend mode, devices must consume no more
than 500 µA (or 2.5 mA for high powered devices that
are remote wake-up capable) from the 5V V
Limiting, see the current Universal Serial Bus Specifi-
cation.
According to the USB 2.0 specification, all USB devices
must also support a Low-Power Suspend mode. In the
USB Suspend mode, devices must consume no more
than 500 µA (or 2.5 mA for high powered devices that
are remote wake-up capable) from the 5V V
BUS
line of
the USB cable.
The host signals the USB device to enter Suspend
mode by stopping all USB traffic to that device for more
than 3 ms.
The USB bus provides a 5V voltage. However, the USB
transceiver requires 3.3V for the signaling (on D+ and
D- lines).
During USB Suspend mode, the D+ or D- pull-up resis-
tor must remain active, which will consume some of the
allowed suspend current budget (500 µA/2.5 mA).
The V
The host signals the USB device to enter Suspend
mode by stopping all USB traffic to that device for more
than 3 ms.
The USB bus provides a 5V voltage. However, the USB
transceiver requires 3.3V for the signaling (on D+ and
D- lines).
During USB Suspend mode, the D+ or D- pull-up resis-
tor must remain active, which will consume some of the
allowed suspend current budget (500 µA/2.5 mA).
The V
USB
pin is required to have an external bypass
capacitor. It is recommended that the capacitor be a
ceramic cap, between 0.22 and 0.47 µF.
ceramic cap, between 0.22 and 0.47 µF.
shows a circuit where the MCP2210 internal
LDO is used to provide 3.3V to the USB transceiver.
The voltage on the V
The voltage on the V
DD
affects the voltage levels onto
the GP and SPI module pins (GP8-GP0, MOSI, MISO
and SCK). With V
and SCK). With V
DD
at 5V, these pins will have a logic
‘1’ of 5V with the variations specified in
.
FIGURE 1-3:
TYPICAL POWER SUPPLY
OPTION USING THE 5V
PROVIDED BY THE USB
OPTION USING THE 5V
PROVIDED BY THE USB
1.5.2.3
3.3V – Self Powered
Typically, many embedded applications are using 3.3V
or lower power supplies. When such an option is avail-
able in the target system, MCP2210 can be powered
up (V
or lower power supplies. When such an option is avail-
able in the target system, MCP2210 can be powered
up (V
DD
) from the existing power supply rail. The typi-
cal connections for MCP2210 powered from 3.3V rail
are shown in
are shown in
In this example MCP2210 has both V
DD
and V
USB
lines
tied to the 3.3V rail. These tied connections disable the
internal USB transceiver LDO of the MCP2210 to
regulate the power supply on V
internal USB transceiver LDO of the MCP2210 to
regulate the power supply on V
USB
pin. Another
consequence is that the ‘1’ logical level on the GP and
SPI pins will be at the 3.3V level, in accordance with the
variations specified in
SPI pins will be at the 3.3V level, in accordance with the
variations specified in
FIGURE 1-4:
USING AN EXTERNALLY
PROVIDED 3.3V POWER
SUPPLY
PROVIDED 3.3V POWER
SUPPLY
LDO
3.3V
3.3V
USB
Transceiver
D+
V
DD
V
USB
D-
IN
OUT
5V (USB Bus)
or external
power supply
LDO
3.3V
3.3V
D+
V
DD
V
USB
D-
IN
OUT
5V (USB Bus)
or external
power supply
External
USB
Transceiver
3.3V
LDO
LDO