Microchip Technology MA330016 Data Sheet
© 2007-2011 Microchip Technology Inc.
DS70290J-page 119
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
TABLE 10-2:
OUTPUT SELECTION FOR REMAPPABLE PIN (RPn)
10.6.3
CONTROLLING CONFIGURATION
CHANGES
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. dsPIC33F devices include three features to
prevent alterations to the peripheral map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit pin select lock
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. dsPIC33F devices include three features to
prevent alterations to the peripheral map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit pin select lock
10.6.3.1
Control Register Lock
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes
appear to execute normally, but the contents of the
registers remain unchanged. To change these
registers, they must be unlocked in hardware. The
register lock is controlled by the IOLOCK bit
(OSCCON<6>). Setting IOLOCK prevents writes to the
control registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
1.
RPORx registers are not allowed. Attempted writes
appear to execute normally, but the contents of the
registers remain unchanged. To change these
registers, they must be unlocked in hardware. The
register lock is controlled by the IOLOCK bit
(OSCCON<6>). Setting IOLOCK prevents writes to the
control registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
1.
Write 0x46 to OSCCON<7:0>.
2.
Write 0x57 to OSCCON<7:0>.
3.
Clear (or set) IOLOCK as a single operation.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the Peripheral Pin Selects to be configured
with a single unlock sequence followed by an update to
all control registers, then locked with a second lock
sequence.
bit, IOLOCK remains in one state until changed. This
allows all of the Peripheral Pin Selects to be configured
with a single unlock sequence followed by an update to
all control registers, then locked with a second lock
sequence.
10.6.3.2
Continuous State Monitoring
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a Configuration Mismatch Reset will
be triggered.
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a Configuration Mismatch Reset will
be triggered.
10.6.3.3
Configuration Bit Pin Select Lock
As an additional level of safety, the device can be
configured to prevent more than one write session to
the RPINRx and RPORx registers. The IOL1WAY
Configuration bit (FOSC<5>) blocks the IOLOCK bit
from being cleared after it has been set once.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows user applications unlimited access
(with the proper use of the unlock sequence) to the
Peripheral Pin Select registers.
configured to prevent more than one write session to
the RPINRx and RPORx registers. The IOL1WAY
Configuration bit (FOSC<5>) blocks the IOLOCK bit
from being cleared after it has been set once.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows user applications unlimited access
(with the proper use of the unlock sequence) to the
Peripheral Pin Select registers.
Function
RPnR<4:0>
Output Name
NULL
00000
RPn tied to default port pin
U1TX
00011
RPn tied to UART1 Transmit
U1RTS
00100
RPn tied to UART1 Ready To Send
SDO1
00111
RPn tied to SPI1 Data Output
SCK1OUT
01000
RPn tied to SPI1 Clock Output
SS1OUT
01001
RPn tied to SPI1 Slave Select Output
OC1
10010
RPn tied to Output Compare 1
OC2
10011
RPn tied to Output Compare 2
Note:
MPLAB
®
C30 provides built-in C
language functions for unlocking the
OSCCON register:
OSCCON register:
__builtin_write_OSCCONL(value)
__builtin_write_OSCCONH(value)
__builtin_write_OSCCONH(value)
See MPLAB
®
IDE Help for more
information.