Microchip Technology MA330016 Data Sheet

Page of 300
© 2007-2011 Microchip Technology Inc.
DS70290J-page 161
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
16.0 INTER-INTEGRATED 
CIRCUIT™ (I
2
C™)
The Inter-Integrated Circuit (I
2
C) module provides
complete hardware support for both Slave and
Multi-Master modes of the I
2
C serial communication
standard, with a 16-bit interface. 
The I
2
C module has a 2-pin interface:
• The SCLx pin is clock
• The SDAx pin is data
The I
2
C module offers the following key features:
• I
2
C interface supporting both Master and Slave 
modes of operation
• I
2
C Slave mode supports 7-bit and 10-bit 
addressing
• I
2
C Master mode supports 7-bit and 10-bit 
addressing
• I
2
C port allows bidirectional transfers between 
master and slaves
• Serial clock synchronization for I
2
C port can be 
used as a handshake mechanism to suspend and 
resume serial transfer (SCLREL control)
• I
2
C supports multi-master operation, detects bus 
collision and arbitrates accordingly
16.1
Operating Modes
The hardware fully implements all the master and slave
functions of the I
2
C Standard and Fast mode
specifications, as well as 7-bit and 10-bit addressing.
The I
2
C module can operate either as a slave or a
master on an I
2
C bus.
The following types of I
2
C operation are supported:
• I
2
C slave operation with 7-bit addressing
• I
2
C slave operation with 10-bit addressing
• I
2
C master operation with 7-bit or 10-bit addressing
For details about the communication sequence in each
of these modes, refer to the “dsPIC33F/PIC24H Family
Reference Manual”
.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GP202/204 and
dsPIC33FJ16GP304 family of devices. It
is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 19. “Inter-Integrated Circuit™
(I
2
C™)” (DS70195) of the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available on the Microchip web
site (
www.microchip.com
).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
 in
this data sheet for device-specific register
and bit information.