Microchip Technology MA330016 Data Sheet
© 2007-2011 Microchip Technology Inc.
DS70290J-page 23
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
REGISTER 3-2:
CORCON: CORE CONTROL REGISTER
U-0
U-0
U-0
R/W-0
R/W-0
R-0
R-0
R-0
—
—
—
US
EDT
(1)
DL<2:0>
bit 15
bit 8
R/W-0
R/W-0
R/W-1
R/W-0
R/C-0
R/W-0
R/W-0
R/W-0
SATA
SATB
SATDW
ACCSAT
IPL3
(2)
PSV
RND
IF
bit 7
bit 0
Legend:
C = Clear only bit
R = Readable bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
0’ = Bit is cleared
‘x = Bit is unknown
U = Unimplemented bit, read as ‘0’
bit 15-13
Unimplemented: Read as ‘0’
bit 12
US: DSP Multiply Unsigned/Signed Control bit
1 = DSP engine multiplies are unsigned
0 = DSP engine multiplies are signed
1 = DSP engine multiplies are unsigned
0 = DSP engine multiplies are signed
bit 11
EDT: Early DO Loop Termination Control bit
(1)
1 = Terminate executing DO loop at end of current loop iteration
0 = No effect
0 = No effect
bit 10-8
DL<2:0>: DO Loop Nesting Level Status bits
111 = 7 DO loops active
•
111 = 7 DO loops active
•
•
•
001 = 1 DO loop active
000 = 0 DO loops active
000 = 0 DO loops active
bit 7
SATA: AccA Saturation Enable bit
1 = Accumulator A saturation enabled
0 = Accumulator A saturation disabled
1 = Accumulator A saturation enabled
0 = Accumulator A saturation disabled
bit 6
SATB: AccB Saturation Enable bit
1 = Accumulator B saturation enabled
0 = Accumulator B saturation disabled
1 = Accumulator B saturation enabled
0 = Accumulator B saturation disabled
bit 5
SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation enabled
0 = Data space write saturation disabled
1 = Data space write saturation enabled
0 = Data space write saturation disabled
bit 4
ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
bit 3
IPL3: CPU Interrupt Priority Level Status bit 3
(2)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
0 = CPU Interrupt Priority Level is 7 or less
bit 2
PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
1 = Program space visible in data space
0 = Program space not visible in data space
bit 1
RND: Rounding Mode Select bit
1 = Biased (conventional) rounding enabled
0 = Unbiased (convergent) rounding enabled
1 = Biased (conventional) rounding enabled
0 = Unbiased (convergent) rounding enabled
bit 0
IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode enabled for DSP multiply ops
0 = Fractional mode enabled for DSP multiply ops
1 = Integer mode enabled for DSP multiply ops
0 = Fractional mode enabled for DSP multiply ops
Note 1: This bit will always read as ‘0’.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.