Microchip Technology MA330011 Data Sheet
©
2007 Microchip Technology Inc.
Preliminary
DS70165E-page 201
dsPIC33F
REGISTER 16-1:
QEICON: QEI CONTROL REGISTER
R/W-0
U-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
CNTERR
—
QEISIDL
INDEX
UPDN
QEIM<2:0>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SWPAB
PCDOUT
TQGATE
TQCKPS<1:0>
POSRES
TQCS
UPDN_SRC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CNTERR: Count Error Status Flag bit
1 = Position count error has occurred
0 = No position count error has occurred
(CNTERR flag only applies when QEIM<2:0> = ‘
1 = Position count error has occurred
0 = No position count error has occurred
(CNTERR flag only applies when QEIM<2:0> = ‘
110
’ or ‘
100
’)
bit 14
Unimplemented: Read as ‘
0
’
bit 13
QEISIDL: Stop in Idle Mode bit
1
= Discontinue module operation when device enters Idle mode
0
= Continue module operation in Idle mode
bit 12
INDEX: Index Pin State Status bit (Read-Only)
1
= Index pin is High
0
= Index pin is Low
bit 11
UPDN: Position Counter Direction Status bit
1
= Position Counter Direction is positive (+)
0
= Position Counter Direction is negative (-)
(Read-only bit when QEIM<2:0> = ‘
1XX
’)
(Read/Write bit when QEIM<2:0> = ‘
001
’)
bit 10-8
QEIM<2:0>: Quadrature Encoder Interface Mode Select bits
111
= Quadrature Encoder Interface enabled (x4 mode) with position counter reset by match (MAXCNT)
110
= Quadrature Encoder Interface enabled (x4 mode) with Index Pulse reset of position counter
101
= Quadrature Encoder Interface enabled (x2 mode) with position counter reset by match (MAXCNT)
100
= Quadrature Encoder Interface enabled (x2 mode) with Index Pulse reset of position counter
011
= Unused (Module disabled)
010
= Unused (Module disabled)
001
= Starts 16-bit Timer
000
= Quadrature Encoder Interface/Timer off
bit 7
SWPAB: Phase A and Phase B Input Swap Select bit
1
= Phase A and Phase B inputs swapped
0
= Phase A and Phase B inputs not swapped
bit 6
PCDOUT: Position Counter Direction State Output Enable bit
1
= Position Counter Direction Status Output Enable (QEI logic controls state of I/O pin)
0
= Position Counter Direction Status Output Disabled (Normal I/O pin operation)
bit 5
TQGATE: Timer Gated Time Accumulation Enable bit
1
= Timer gated time accumulation enabled
0
= Timer gated time accumulation disabled