Microchip Technology MA330011 Data Sheet

Page of 370
©
 2007 Microchip Technology Inc.
Preliminary
DS70165E-page 229
dsPIC33F
bit 4
RIDLE: Receiver Idle bit (read-only)
1
 = Receiver is Idle
0
 = Receiver is active
bit 3
PERR: Parity Error Status bit (read-only)
1
 = Parity error has been detected for the current character (character at the top of the receive FIFO)
0
 = Parity error has not been detected
bit 2
FERR: Framing Error Status bit (read-only)
1
 = Framing error has been detected for the current character (character at the top of the receive
FIFO)
0
 = Framing error has not been detected
bit 1
OERR: Receive Buffer Overrun Error Status bit (read/clear only)
1
 = Receive buffer has overflowed
0
 = Receive buffer has not overflowed. Clearing a previously set OERR bit (
1
→ 0
 transition) will reset
the receiver buffer and the UxRSR to the empty state.
bit 0
URXDA: Receive Buffer Data Available bit (read-only)
1
 = Receive buffer has data, at least one more character can be read
0
 = Receive buffer is empty
REGISTER 19-2:
U
x
STA: UART
x
 STATUS AND CONTROL REGISTER (CONTINUED)
Note 1:
Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled 
(IREN =
1
).