Microchip Technology MA330011 Data Sheet
dsPIC33F
DS70165E-page 264
Preliminary
©
2007 Microchip Technology Inc.
21.3.6
SLAVE FRAME SYNC OPERATION
When the DCI module is operating as a frame sync
slave (COFSD =
slave (COFSD =
1
), data transfers are controlled by the
Codec device attached to the DCI module. The
COFSM control bits control how the DCI module
responds to incoming COFS signals.
COFSM control bits control how the DCI module
responds to incoming COFS signals.
In the Multi-Channel mode, a new data frame transfer
will begin one CSCK cycle after the COFS pin is sam-
pled high (see Figure 21-2). The pulse on the COFS
pin resets the frame sync generator logic.
will begin one CSCK cycle after the COFS pin is sam-
pled high (see Figure 21-2). The pulse on the COFS
pin resets the frame sync generator logic.
In the I
2
S mode, a new data word will be transferred
one CSCK cycle after a low-to-high or a high-to-low
transition is sampled on the COFS pin. A rising or fall-
ing edge on the COFS pin resets the frame sync
generator logic.
transition is sampled on the COFS pin. A rising or fall-
ing edge on the COFS pin resets the frame sync
generator logic.
In the AC-Link mode, the tag slot and subsequent data
slots for the next frame will be transferred one CSCK
cycle after the COFS pin is sampled high.
slots for the next frame will be transferred one CSCK
cycle after the COFS pin is sampled high.
The COFSG and WS bits must be configured to pro-
vide the proper frame length when the module is oper-
ating in the Slave mode. Once a valid frame sync pulse
has been sampled by the module on the COFS pin, an
entire data frame transfer will take place. The module
will not respond to further frame sync pulses until the
data frame transfer has completed.
vide the proper frame length when the module is oper-
ating in the Slave mode. Once a valid frame sync pulse
has been sampled by the module on the COFS pin, an
entire data frame transfer will take place. The module
will not respond to further frame sync pulses until the
data frame transfer has completed.
FIGURE 21-2:
FRAME SYNC TIMING, MULTI-CHANNEL MODE
FIGURE 21-3:
FRAME SYNC TIMING, AC-LINK START-OF-FRAME
FIGURE 21-4:
I
2
S INTERFACE FRAME SYNC TIMING
CSCK
CSDI/CSDO
COFS
MSb
LSb
Tag
MSb
BIT_CLK
CSDO or CSDI
SYNC
Tag
bit 14
S12
LSb
S12
bit 1
S12
bit 2
Tag
bit 13
MSb
LSb
MSb
LSb
CSCK
CSDI or CSDO
WS
Note:
A 5-bit transfer is shown here for illustration purposes. The I
2
S protocol does not specify word length – this
will be system dependent.