Microchip Technology MA330011 Data Sheet
©
2007 Microchip Technology Inc.
Preliminary
DS70165E-page 33
dsPIC33F
2.5
Arithmetic Logic Unit (ALU)
The dsPIC33F ALU is 16 bits wide and is capable of
addition, subtraction, bit shifts and logic operations.
Unless otherwise mentioned, arithmetic operations are
2’s complement in nature. Depending on the operation,
the ALU may affect the values of the Carry (C), Zero
(Z), Negative (N), Overflow (OV) and Digit Carry (DC)
Status bits in the SR register. The C and DC Status bits
operate as Borrow and Digit Borrow bits, respectively,
for subtraction operations.
addition, subtraction, bit shifts and logic operations.
Unless otherwise mentioned, arithmetic operations are
2’s complement in nature. Depending on the operation,
the ALU may affect the values of the Carry (C), Zero
(Z), Negative (N), Overflow (OV) and Digit Carry (DC)
Status bits in the SR register. The C and DC Status bits
operate as Borrow and Digit Borrow bits, respectively,
for subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W reg-
ister array, or data memory, depending on the address-
ing mode of the instruction. Likewise, output data from
the ALU can be written to the W register array or a data
memory location.
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W reg-
ister array, or data memory, depending on the address-
ing mode of the instruction. Likewise, output data from
the ALU can be written to the W register array or a data
memory location.
Refer to the “dsPIC30F/33F Programmer’s Reference
Manual” (DS70157) for information on the SR bits
affected by each instruction.
Manual” (DS70157) for information on the SR bits
affected by each instruction.
The dsPIC33F CPU incorporates hardware support for
both multiplication and division. This includes a dedi-
cated hardware multiplier and support hardware for
16-bit-divisor division.
both multiplication and division. This includes a dedi-
cated hardware multiplier and support hardware for
16-bit-divisor division.
2.5.1
MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier of the DSP
engine, the ALU supports unsigned, signed or mixed-sign
operation in several MCU multiplication modes:
engine, the ALU supports unsigned, signed or mixed-sign
operation in several MCU multiplication modes:
1.
16-bit x 16-bit signed
2.
16-bit x 16-bit unsigned
3.
16-bit signed x 5-bit (literal) unsigned
4.
16-bit unsigned x 16-bit unsigned
5.
16-bit unsigned x 5-bit (literal) unsigned
6.
16-bit unsigned x 16-bit signed
7.
8-bit unsigned x 8-bit unsigned
2.5.2
DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
signed and unsigned integer divide operations with the
following data sizes:
1.
32-bit signed/16-bit signed divide
2.
32-bit unsigned/16-bit unsigned divide
3.
16-bit signed/16-bit signed divide
4.
16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
and the remainder in W1. 16-bit signed and unsigned
DIV
instructions can specify any W register for both the
16-bit divisor (Wn) and any W register (aligned) pair
(W(m + 1):Wm) for the 32-bit dividend. The divide algo-
rithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
(W(m + 1):Wm) for the 32-bit dividend. The divide algo-
rithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
2.6
DSP Engine
The DSP engine consists of a high-speed, 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit
adder/subtracter (with two target accumulators, round
and saturation logic).
17-bit multiplier, a barrel shifter and a 40-bit
adder/subtracter (with two target accumulators, round
and saturation logic).
The dsPIC33F is a single-cycle, instruction flow architec-
ture; therefore, concurrent operation of the DSP engine
with MCU instruction flow is not possible. However, some
MCU ALU and DSP engine resources may be used
concurrently by the same instruction (e.g., ED, EDAC).
ture; therefore, concurrent operation of the DSP engine
with MCU instruction flow is not possible. However, some
MCU ALU and DSP engine resources may be used
concurrently by the same instruction (e.g., ED, EDAC).
The DSP engine also has the capability to perform
inherent accumulator-to-accumulator operations which
require no additional data. These instructions are
inherent accumulator-to-accumulator operations which
require no additional data. These instructions are
ADD,
SUB
and
NEG
.
The DSP engine has various options selected through
various bits in the CPU Core Control register
(CORCON), as listed below:
various bits in the CPU Core Control register
(CORCON), as listed below:
1.
Fractional or integer DSP multiply (IF).
2.
Signed or unsigned DSP multiply (US).
3.
Conventional or convergent rounding (RND).
4.
Automatic saturation on/off for AccA (SATA).
5.
Automatic saturation on/off for AccB (SATB).
6.
Automatic saturation on/off for writes to data
memory (SATDW).
memory (SATDW).
7.
Accumulator Saturation mode selection (ACCSAT).
A block diagram of the DSP engine is shown in
Figure 2-3.
Figure 2-3.
TABLE 2-1:
DSP INSTRUCTIONS SUMMARY
Instruction
Algebraic Operation
ACC Write Back
CLR
A = 0
Yes
ED
A = (x – y)
2
No
EDAC
A = A + (x – y)
2
No
MAC
A = A + (x * y)
Yes
MAC
A = A + x
2
No
MOVSAC
No change in A
Yes
MPY
A = x * y
No
MPY
A = x
2
No
MPY.N
A = – x * y
No
MSC
A = A – x * y
Yes