Microchip Technology AC244049 Data Sheet

PIC16F72X/PIC16LF72X

DS41341E-page 162

FIGURE 16-8:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

TABLE 16-7:

REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

INTCON

GIE PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

PIE1

TMR1GIE

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

PIR1

TMR1GIF

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

RCREG

AUSART Receive Data Register

0000 0000

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000X

TRISC

TRISC7

TRISC6

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

1111 1111

TXSTA

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

0000 -010

Legend:

= unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.

CREN bit

RX/DT

Write to

bit SREN

SREN bit

RCIF bit

(Interrupt)

Read

RCREG

‘0’

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

‘0’

Note:

Timing diagram demonstrates Synchronous Master mode with bit SREN = 1 and bit BRGH = 0.

TX/CK pin