Microchip Technology AC244049 Data Sheet

© 2009 Microchip Technology Inc.

DS41341E-page 173

17.1.2.4

Slave Select Operation

The SS pin allows Synchronous Slave mode operation.
The SPI must be in Slave mode with SS pin control
enabled (SSPM<3:0> = 0100). The associated TRIS bit
for the SS pin must be set, making SS an input.

In Slave Select mode, when:

• SS = 0, The device operates as specified in 

Section 17.1.2 “Slave Mode”.

• SS = 1, The SPI module is held in Reset and the 

SDO pin will be tri-stated.

When the SPI module resets, the bit counter is cleared
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit. Figure 17-6
shows the timing waveform for such a synchronization
event.

17.1.2.5

Sleep in Slave Mode

While in Sleep mode, the slave can transmit/receive
data. The SPI Transmit/Receive Shift register operates
asynchronously to the device on the externally supplied
clock source. This allows the device to be placed in
Sleep mode and data to be shifted into the SPI Trans-
mit/Receive Shift register. When all 8 bits have been
received, the SSP Interrupt Flag bit will be set and if
enabled, will wake the device from Sleep.

Note 1: When the SPI is in Slave mode with SS pin

control enabled (SSPM<3:0> = 0100), the
SPI module will reset if the SS pin is driven
high.

2: If the SPI is used in Slave mode with CKE

set, the SS pin control must be enabled.

SSPSR must be reinitialized by writing to
the SSPBUF register before the data can
be clocked out of the slave again.

SCK
(CKP = 1

SCK
(CKP = 0

Input
Sample

SDI

bit 7

SDO

bit 7

bit 6

bit 7

SSPIF

Interrupt 

(SMP = 0)

CKE = 0)

CKE = 0)

(SMP = 0)

Write to
SSPBUF

SSPSR to
SSPBUF

SS

Flag

bit 0

bit 7

bit 0

SSPSR must be reinitialized by writing to
the SSPBUF register before the data can
be clocked out of the slave again.