Microchip Technology AC244049 Data Sheet
PIC16F72X/PIC16LF72X
DS41341E-page 186
© 2009 Microchip Technology Inc.
REGISTER 17-3:
SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER (I
2
C MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit
1
= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0
= No collision
bit 6
SSPOV: Receive Overflow Indicator bit
1
= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t
care” in Transmit mode. SSPOV must be cleared in software in either mode.
0
= No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
1
= Enables the serial port and configures the SDA and SCL pins as serial port pins
(2)
0
= Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
1
= Release control of SCL
0
= Holds clock low (clock stretch). (Used to ensure data setup time.)
bit 3-0
SSPM<3:0>: Synchronous Serial Port Mode Select bits
0110
= I
2
C Slave mode, 7-bit address
0111
= I
2
C Slave mode, 10-bit address
1000
= Reserved
1001
= Load SSPMSK register at SSPADD SFR Address
(1)
1010
= Reserved
1011
= I
2
C Firmware Controlled Master mode (Slave Idle)
1100
= Reserved
1101
= Reserved
1110
= I
2
C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111
= I
2
C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
Note 1: When this mode is selected, any reads or writes to the SSPADD SFR address accesses the SSPMSK register.
2: When enabled, these pins must be properly configured as input or output using the associated TRIS bit.