Microchip Technology MCP3421DM-WS Data Sheet
© 2009 Microchip Technology Inc.
DS39632E-page 135
PIC18F2455/2550/4455/4550
12.7
Considerations in Asynchronous
Counter Mode
Counter Mode
Following a Timer1 interrupt and an update to the
TMR1 registers, the Timer1 module uses a falling edge
on its clock source to trigger the next register update on
the rising edge. If the update is completed after the
clock input has fallen, the next rising edge will not be
counted.
If the application can reliably update TMR1 before the
timer input goes low, no additional action is needed.
Otherwise, an adjusted update can be performed
TMR1 registers, the Timer1 module uses a falling edge
on its clock source to trigger the next register update on
the rising edge. If the update is completed after the
clock input has fallen, the next rising edge will not be
counted.
If the application can reliably update TMR1 before the
timer input goes low, no additional action is needed.
Otherwise, an adjusted update can be performed
following a later Timer1 increment. This can be done
by monitoring TMR1L within the interrupt routine until it
increments, and then updating the TMR1H:TMR1L reg-
ister pair while the clock is low, or one-half of the period
of the clock source. Assuming that Timer1 is being
used as a Real-Time Clock, the clock source is a
32.768 kHz crystal oscillator; in this case, one-half
period of the clock is 15.25
by monitoring TMR1L within the interrupt routine until it
increments, and then updating the TMR1H:TMR1L reg-
ister pair while the clock is low, or one-half of the period
of the clock source. Assuming that Timer1 is being
used as a Real-Time Clock, the clock source is a
32.768 kHz crystal oscillator; in this case, one-half
period of the clock is 15.25
μs.
The Real-Time Clock application code in Example 12-1
shows a typical ISR for Timer1, as well as the optional
code required if the update cannot be done reliably
within the required interval.
shows a typical ISR for Timer1, as well as the optional
code required if the update cannot be done reliably
within the required interval.
EXAMPLE 12-1:
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW
80h
; Preload TMR1 register pair
MOVWF
TMR1H
; for 1 second overflow
CLRF
TMR1L
MOVLW
b’00001111’
; Configure for external clock,
MOVWF
T1CON
; Asynchronous operation, external oscillator
CLRF
secs
; Initialize timekeeping registers
CLRF
mins
;
MOVLW
.12
MOVWF
hours
BSF
PIE1, TMR1IE
; Enable Timer1 interrupt
RETURN
RTCisr
; Insert the next 4 lines of code when TMR1
; can not be reliably updated before clock pulse goes low
; can not be reliably updated before clock pulse goes low
BTFSC
TMR1L,0
; wait for TMR1L to become clear
BRA
$-2
; (may already be clear)
BTFSS
TMR1L,0
; wait for TMR1L to become set
BRA
$-2
; TMR1 has just incremented
; If TMR1 update can be completed before clock pulse goes low
; Start ISR here
; If TMR1 update can be completed before clock pulse goes low
; Start ISR here
BSF
TMR1H, 7
; Preload for 1 sec overflow
BCF
PIR1, TMR1IF
; Clear interrupt flag
INCF
secs, F
; Increment seconds
MOVLW
.59
; 60 seconds elapsed?
CPFSGT secs
RETURN
RETURN
; No, done
CLRF
secs
; Clear seconds
INCF
mins, F
; Increment minutes
MOVLW
.59
; 60 minutes elapsed?
CPFSGT mins
RETURN
RETURN
; No, done
CLRF
mins
; clear minutes
INCF
hours, F
; Increment hours
MOVLW
.23
; 24 hours elapsed?
CPFSGT hours
RETURN
RETURN
; No, done
CLRF
hours
; Reset hours
RETURN
; Done