Microchip Technology MCP3421DM-WS Data Sheet
© 2009 Microchip Technology Inc.
DS39632E-page 147
PIC18F2455/2550/4455/4550
TABLE 15-3:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
RCON
IPEN
SBOREN
(1)
—
RI
TO
PD
POR
BOR
PIR1
SPPIF
(2)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
PIE1
SPPIE
(2)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
IPR1
SPPIP
(2)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
PIR2
OSCFIF
CMIF
USBIF
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF
PIE2
OSCFIE
CMIE
USBIE
EEIE
BCLIE
HLVDIE
TMR3IE
CCP2IE
IPR2
OSCFIP
CMIP
USBIP
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
TRISC
TRISC7
TRISC6
—
—
—
TRISC2
TRISC1
TRISC0
TMR1L
Timer1 Register Low Byte
TMR1H
Timer1 Register High Byte
T1CON
RD16
T1RUN
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
TMR3H
Timer3 Register High Byte
TMR3L
Timer3 Register Low Byte
T3CON
RD16
T3CCP2
T3CKPS1 T3CKPS0 T3CCP1
T3SYNC TMR3CS TMR3ON
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
CCPR1H
Capture/Compare/PWM Register 1 High Byte
CCP1CON
P1M1
(2)
P1M0
(2)
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
CCPR2H
Capture/Compare/PWM Register 2 High Byte
CCP2CON
—
—
DC2B1
DC2B0
CCP2M3 CCP2M2 CCP2M1 CCP2M0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3.
Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
2: These bits are unimplemented on 28-pin devices; always maintain these bits clear.