Microchip Technology MCP3421DM-WS Data Sheet
© 2009 Microchip Technology Inc.
DS39632E-page 179
PIC18F2455/2550/4455/4550
TABLE 17-4:
ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT
BUFFERING MODES
BUFFERING MODES
TABLE 17-5:
SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS
Endpoint
BDs Assigned to Endpoint
Mode 0
(No Ping-Pong)
Mode 1
(Ping-Pong on EP0 OUT)
Mode 2
(Ping-Pong on all EPs)
Mode 3
(Ping-Pong on all other EPs,
except EP0)
Out
In
Out
In
Out
In
Out
In
0
0
1
0 (E), 1 (O)
2
0 (E), 1 (O)
2 (E), 3 (O)
0
1
1
2
3
3
4
4 (E), 5 (O)
6 (E), 7 (O)
2 (E), 3 (O)
4 (E), 5 (O)
2
4
5
5
6
8 (E), 9 (O)
10 (E), 11 (O)
6 (E), 7 (O)
8 (E), 9 (O)
3
6
7
7
8
12 (E), 13 (O)
14 (E), 15 (O) 10 (E), 11 (O) 12 (E), 13 (O)
4
8
9
9
10
16 (E), 17 (O)
18 (E), 19 (O) 14 (E), 15 (O) 16 (E), 17 (O)
5
10
11
11
12
20 (E), 21 (O)
22 (E), 23 (O) 18 (E), 19 (O) 20 (E), 21 (O)
6
12
13
13
14
24 (E), 25 (O)
26 (E), 27 (O) 22 (E), 23 (O) 24 (E), 25 (O)
7
14
15
15
16
28 (E), 29 (O)
30 (E), 31 (O) 26 (E), 27 (O) 28 (E), 29 (O)
8
16
17
17
18
32 (E), 33 (O)
34 (E), 35 (O) 30 (E), 31 (O) 32 (E), 33 (O)
9
18
19
19
20
36 (E), 37 (O)
38 (E), 39 (O) 34 (E), 35 (O) 36 (E), 37 (O)
10
20
21
21
22
40 (E), 41 (O)
42 (E), 43 (O) 38 (E), 39 (O) 40 (E), 41 (O)
11
22
23
23
24
44 (E), 45 (O)
46 (E), 47 (O) 42 (E), 43 (O) 44 (E), 45 (O)
12
24
25
25
26
48 (E), 49 (O)
50 (E), 51 (O) 46 (E), 47 (O) 48 (E), 49 (O)
13
26
27
27
28
52 (E), 53 (O)
54 (E), 55 (O) 50 (E), 51 (O) 52 (E), 53 (O)
14
28
29
29
30
56 (E), 57 (O)
58 (E), 59 (O) 54 (E), 55 (O) 56 (E), 57 (O)
15
30
31
31
32
60 (E), 61 (O)
62 (E), 63 (O) 58 (E), 59 (O) 60 (E), 61 (O)
Legend:
(E) = Even transaction buffer, (O) = Odd transaction buffer
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BDnSTAT
(1)
UOWN
DTS
(4)
PID3
(2)
KEN
(3)
PID2
(2)
INCDIS
(3)
PID1
(2)
DTSEN
(3)
PID0
(2)
BSTALL
(3)
BC9
BC8
BDnCNT
(1)
Byte Count
BDnADRL
(1)
Buffer Address Low
BDnADRH
(1)
Buffer Address High
Note 1:
For buffer descriptor registers, n may have a value of 0 to 63. For the sake of brevity, all 64 registers are
shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx).
shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx).
2:
Bits 5 through 2 of the BDnSTAT register are used by the SIE to return PID3:PID0 values once the register
is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values
written for KEN, INCDIS, DTSEN and BSTALL are no longer valid.
is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values
written for KEN, INCDIS, DTSEN and BSTALL are no longer valid.
3:
Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 5 through 2 of the
BDnSTAT register are used to configure the KEN, INCDIS, DTSEN and BSTALL settings.
BDnSTAT register are used to configure the KEN, INCDIS, DTSEN and BSTALL settings.
4:
This bit is ignored unless DTSEN = 1.