Microchip Technology MCP3421DM-WS Data Sheet

DS39632E-page 236

 

© 2009 Microchip Technology Inc.

19.4.14

SLEEP OPERATION

While in Sleep mode, the I

2

C module can receive

addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).

19.4.15

EFFECTS OF A RESET

A Reset disables the MSSP module and terminates the
current transfer.

19.4.16

MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I

2

C bus may

be taken when the P bit (SSPSTAT<4>) is set, or the
bus is Idle, with both the S and P bits clear. When the
bus is busy, enabling the MSSP interrupt will generate
the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer 
• Data Transfer
• A Start Condition 
• A Repeated Start Condition
• An Acknowledge Condition

19.4.17

MULTI -MASTER COMMUNICATION, 
BUS COLLISION AND BUS 
ARBITRATION

Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF, and reset the
I

2

C port to its Idle state (Figure 19-27).

If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine, and if the I

2

C

bus is free, the user can resume communication by
asserting a Start condition. 
If a Start, Repeated Start, Stop or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are deasserted and the respective control bits in
the SSPCON2 register are cleared. When the user ser-
vices the bus collision Interrupt Service Routine, and if
the I

2

C bus is free, the user can resume communication

by asserting a Start condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPBUF bit will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determi-
nation of when the bus is free. Control of the I

2

C bus can

be taken when the P bit is set in the SSPSTAT register,
or the bus is Idle and the S and P bits are cleared.

SDA

SCL

BCLIF

SDA released

SDA line pulled low

by another source

Sample SDA. While SCL is high,

data doesn’t match what is driven 

Bus collision has occurred.

Set Bus Collision
Interrupt Flag (BCLIF)

by the master.

by master

Data changes
while SCL = 0