Microchip Technology MCP3421DM-WS Data Sheet
PIC18F2455/2550/4455/4550
DS39632E-page 262
© 2009 Microchip Technology Inc.
20.3.2
EUSART SYNCHRONOUS
MASTER RECEPTION
MASTER RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA<5>), or the Continuous Receive
Enable bit, CREN (RCSTA<4>). Data is sampled on the
RX pin on the falling edge of the clock.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1.
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA<5>), or the Continuous Receive
Enable bit, CREN (RCSTA<4>). Data is sampled on the
RX pin on the falling edge of the clock.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1.
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
2.
Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
setting bits, SYNC, SPEN and CSRC.
3.
Ensure bits, CREN and SREN, are clear.
4.
If the signal from the CK pin is to be inverted, set
the TXCKP bit. If the signal from the DT pin is to
be inverted, set the RXDTP bit.
the TXCKP bit. If the signal from the DT pin is to
be inverted, set the RXDTP bit.
5.
If interrupts are desired, set enable bit, RCIE.
6.
If 9-bit reception is desired, set bit, RX9.
7.
If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
For continuous reception, set bit, CREN.
8.
Interrupt flag bit, RCIF, will be set when reception
is complete and an interrupt will be generated if
the enable bit, RCIE, was set.
is complete and an interrupt will be generated if
the enable bit, RCIE, was set.
9.
Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
enabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RCREG register.
11. If any error occurred, clear the error by clearing
bit, CREN.
12. If using interrupts, ensure that the GIE and PEIE bits
in the INTCON register (INTCON<7:6>) are set.
FIGURE 20-13:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 20-8:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on page
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
SPPIF
(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
PIE1
SPPIE
(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
IPR1
SPPIP
(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
RCREG
EUSART Receive Register
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
BAUDCON ABDOVF
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
SPBRGH
EUSART Baud Rate Generator Register High Byte
SPBRG
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
CREN bit
RC7/RX/DT/SDO
RC6/TX/CK pin
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘0’
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
‘0’
Q1 Q2 Q3 Q4
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
RC6/TX/CK pin
pin
(TXCKP = 0)
(TXCKP = 1)