Microchip Technology MCP3421DM-WS Data Sheet
© 2009 Microchip Technology Inc.
DS39632E-page 273
PIC18F2455/2550/4455/4550
21.6
A/D Conversions
Figure 21-4 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 21-5 shows the operation of the A/D converter
after the GO/DONE bit has been set, the
ACQT2:ACQT0 bits are set to ‘010’ and selecting a
4 T
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 21-5 shows the operation of the A/D converter
after the GO/DONE bit has been set, the
ACQT2:ACQT0 bits are set to ‘010’ and selecting a
4 T
AD
acquisition time before the conversion starts.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. This means the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. This means the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
2 T
CY
wait is required before the next acquisition can be
started. After this wait, acquisition on the selected
channel is automatically started.
channel is automatically started.
21.7
Discharge
The discharge phase is used to initialize the value of
the capacitor array. The array is discharged before
every sample. This feature helps to optimize the
unity-gain amplifier as the circuit always needs to
charge the capacitor array, rather than
charge/discharge based on previous measurement
values.
the capacitor array. The array is discharged before
every sample. This feature helps to optimize the
unity-gain amplifier as the circuit always needs to
charge the capacitor array, rather than
charge/discharge based on previous measurement
values.
FIGURE 21-4:
A/D CONVERSION T
AD
CYCLES (ACQT<2:0> = 000, T
ACQ
= 0)
FIGURE 21-5:
A/D CONVERSION T
AD
CYCLES (ACQT<2:0> = 010, T
ACQ
= 4 T
AD
)
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Code should wait at least 2 µs after
enabling the A/D before beginning an
acquisition and conversion cycle.
the same instruction that turns on the A/D.
Code should wait at least 2 µs after
enabling the A/D before beginning an
acquisition and conversion cycle.
T
AD
1 T
AD
2 T
AD
3 T
AD
4 T
AD
5 T
AD
6 T
AD
7 T
AD
8
T
AD
11
Set GO/DONE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
T
AD
9 T
AD
10
T
CY
- T
AD
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b0
b9
b6
b5
b4
b3
b2
b1
b8
b7
On the following cycle:
T
AD
1
Discharge
(Typically 200 ns)
(Typically 200 ns)
1
2
3
4
5
6
7
8
11
Set GO/DONE bit
(Holding capacitor is disconnected)
9
10
Conversion starts
1
2
3
4
(Holding capacitor continues
acquiring input)
acquiring input)
T
ACQ
Cycles
T
AD
Cycles
Automatic
Acquisition
Time
b0
b9
b6
b5
b4
b3
b2
b1
b8
b7
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
ADIF bit is set, holding capacitor is connected to analog input.
On the following cycle:
T
AD
1
Discharge
(Typically
200 ns)
(Typically
200 ns)