Microchip Technology MCP3421DM-WS Data Sheet
PIC18F2455/2550/4455/4550
DS39632E-page 282
© 2009 Microchip Technology Inc.
FIGURE 23-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
23.2
Voltage Reference Accuracy/Error
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 23-1) keep CV
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 23-1) keep CV
REF
from approaching the refer-
ence source rails. The voltage reference is derived
from the reference source; therefore, the CV
from the reference source; therefore, the CV
REF
output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 28.0 “Electrical Characteristics”.
absolute accuracy of the voltage reference can be
found in Section 28.0 “Electrical Characteristics”.
23.3
Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
23.4
Effects of a Reset
A device Reset disables the voltage reference by
clearing bit, CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RA2 pin by clearing
bit, CVROE (CVRCON<6>) and selects the high-voltage
range by clearing bit, CVRR (CVRCON<5>). The CVR
value select bits are also cleared.
clearing bit, CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RA2 pin by clearing
bit, CVROE (CVRCON<6>) and selects the high-voltage
range by clearing bit, CVRR (CVRCON<5>). The CVR
value select bits are also cleared.
23.5
Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RA2 pin if the
TRISA<2> bit and the CVROE bit are both set.
Enabling the voltage reference output onto RA2 when
it is configured as a digital input will increase current
consumption. Connecting RA2 as a digital output with
CVRSS enabled will also increase current
consumption.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage
reference output for external connections to V
of the comparator module. The output of the reference
generator may be connected to the RA2 pin if the
TRISA<2> bit and the CVROE bit are both set.
Enabling the voltage reference output onto RA2 when
it is configured as a digital input will increase current
consumption. Connecting RA2 as a digital output with
CVRSS enabled will also increase current
consumption.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage
reference output for external connections to V
REF
.
Figure 23-2 shows an example buffering technique.
16-
to
-1 MUX
CVR3:CVR0
8R
R
CVREN
CVRSS = 0
V
DD
V
REF
+
CVRSS = 1
8R
CVRSS = 0
V
REF
-
CVRSS = 1
R
R
R
R
R
R
16 Steps
CVRR
CV
REF