Microchip Technology MCP3421DM-WS Data Sheet
© 2009 Microchip Technology Inc.
DS39632E-page 401
PIC18F2455/2550/4455/4550
FIGURE 28-19:
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 28-23: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 28-20:
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 28-24: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
121
121
120
122
RC6/TX/CK
RC7/RX/DT/SDO
pin
pin
Note:
Refer to Figure 28-4 for load conditions.
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
120
TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid
PIC18FXXXX
—
40
ns
PIC18LFXXXX
—
100
ns
V
DD
= 2.0V
121
Tckrf
Clock Out Rise Time and Fall Time
(Master mode)
(Master mode)
PIC18FXXXX
—
20
ns
PIC18LFXXXX
—
50
ns
V
DD
= 2.0V
122
Tdtrf
Data Out Rise Time and Fall Time
PIC18FXXXX
—
20
ns
PIC18LFXXXX
—
50
ns
V
DD
= 2.0V
125
126
RC6/TX/CK
RC7/RX/DT/SDO
pin
pin
Note:
Refer to Figure 28-4 for load conditions.
Param.
No.
Symbol
Characteristic
Min
Max
Units
Conditions
125
T
DT
V2
CKL
SYNC RCV (MASTER & SLAVE)
Data Hold before CK
Data Hold before CK
↓ (DT hold time)
10
—
ns
126
T
CK
L2
DTL
Data Hold after CK
↓ (DT hold time)
15
—
ns