Microchip Technology MCP3421DM-WS Data Sheet
© 2009 Microchip Technology Inc.
DS39632E-page 43
PIC18F2455/2550/4455/4550
3.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped; and
• the primary clock source is not any of the XT or
HS modes.
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (EC and any internal
oscillator modes). However, a fixed delay of interval
T
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (EC and any internal
oscillator modes). However, a fixed delay of interval
T
CSD
following the wake event is still required when
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
TABLE 3-2:
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
(BY CLOCK SOURCES)
Microcontroller Clock Source
Exit Delay
Clock Ready Status
Bit (OSCCON)
Before Wake-up
After Wake-up
Primary Device Clock
(PRI_IDLE mode)
XT, HS
None
OSTS
XTPLL, HSPLL
EC
INTOSC
(3)
IOFS
T1OSC or INTRC
(1)
XT, HS
T
OST(4)
OSTS
XTPLL, HSPLL
T
OST
+ t
rc
(4)
EC
T
CSD(2)
INTOSC
(3)
T
IOBST(5)
IOFS
INTOSC
(3)
XT, HS
T
OST(4)
OSTS
XTPLL, HSPLL
T
OST
+ t
rc
(4)
EC
T
CSD(2)
INTOSC
(3)
None
IOFS
None
(Sleep mode)
XT, HS
T
OST(4)
OSTS
XTPLL, HSPLL
T
OST
+ t
rc
(4)
EC
T
CSD(2)
INTOSC
(3)
T
IOBST(5)
IOFS
Note 1:
In this instance, refers specifically to the 31 kHz INTRC clock source.
2:
T
CSD
(parameter 38, Table 28-12) is a required delay when waking from Sleep and all Idle modes and runs
concurrently with any other required delays (see Section 3.4 “Idle Modes”).
3:
Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
4:
T
OST
is the Oscillator Start-up Timer period (parameter 32, Table 28-12). t
rc
is the PLL lock time-out
(parameter F12, Table 28-9); it is also designated as T
PLL
.
5:
Execution continues during T
IOBST
(parameter 39, Table 28-12), the INTOSC stabilization period.