Microchip Technology DM164130-7 Data Sheet

 2010-2012 Microchip Technology Inc.

DS41414D-page 219

23.2.5

COMPARE DURING SLEEP

The Compare mode is dependent upon the system
clock (F

OSC

) for proper operation. Since F

OSC

 is shut

down during Sleep mode, the Compare mode will not
function properly during Sleep.

23.2.6

ALTERNATE PIN LOCATIONS

This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
reset, see 

 for

more information.

CCPxCON

PxM<1:0>

DCxB<1:0>

CCPxM<3:0>

CCPRxL

Capture/Compare/PWM Register x Low Byte (LSB)

CCPRxH

Capture/Compare/PWM Register x High Byte (MSB)

INTCON

GIE PEIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

IOCIF

PIE1

TMR1GIE

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

PIE2

OSFIE

C2IE

C1IE

EEIE

BCLIE

LCDIE

C3IE

CCP2IE

PIE3

—

CCP5IE

CCP4IE

CCP3IE

TMR6IE

—

TMR4IE

—

PIR1

TMR1GIF

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

PIR2

OSFIF

C2IF

C1IF

EEIF

BCLIF

LCDIF

C31F

CCP2IF

PIR3

—

CCP5IF

CCP4IF

CCP3IF

TMR6IF

—

TMR4IF

—

T1CON

TMR1CS<1:0>

T1CKPS<1:0>

T1OSCEN

T1SYNC

—

TMR1ON

T1GCON

TMR1GE

T1GPOL

T1GTM

T1GSPM

T1GGO/DONE

T1GVAL

T1GSS<1:0>

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

TMR1H

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

TRISA

TRISA7

TRISA6

TRISA5

TRISA4

TRISA3

TRISA2

TRISA1

TRISA0

TRISB

TRISB7

TRISB6

TRISB5

TRISB4

TRISB3

TRISB2

TRISB1

TRISB0

TRISC

TRISC7

TRISC6

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

TRISD

TRISD7

TRISD6

TRISD5

TRISD4

TRISD3

TRISD2

TRISD1

TRISD0

TRISE

TRISE7

TRISE6

TRISE5

TRISE4

TRISE3

TRISE2

TRISE1

TRISE0

Legend:  — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode.
Note 1:

Applies to ECCP modules only.

*

Page provides register information.