Microchip Technology DM164130-7 Data Sheet
PIC16(L)F1946/1947
DS41414D-page 24
2010-2012 Microchip Technology Inc.
3.1.1.2
Indirect Read with FSR
The program memory can be accessed as data by set-
ting bit 7 of the FSRxH register and reading the match-
ing INDFx register. The MOVIW instruction will place the
lower 8 bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the pro-
gram memory via the FSR require one extra instruction
cycle to complete.
ting bit 7 of the FSRxH register and reading the match-
ing INDFx register. The MOVIW instruction will place the
lower 8 bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the pro-
gram memory via the FSR require one extra instruction
cycle to complete.
demonstrates access-
ing the program memory via an FSR.
The HIGH directive will set bit<7> if a label points to a
location in program memory.
The HIGH directive will set bit<7> if a label points to a
location in program memory.
EXAMPLE 3-2:
ACCESSING PROGRAM
MEMORY VIA FSR
MEMORY VIA FSR
3.2
Data Memory Organization
):
• 12 core registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See
for more information.
Data Memory uses a 12-bit address. The upper 7-bits
of the address define the Bank address and the lower
5-bits select the registers/RAM in that bank.
of the address define the Bank address and the lower
5-bits select the registers/RAM in that bank.
3.2.1
CORE REGISTERS
The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These reg-
isters are listed below in
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These reg-
isters are listed below in
. For detailed infor-
TABLE 3-2:
CORE REGISTERS
constants
RETLW DATA0
;Index0 data
RETLW DATA1
;Index1 data
RETLW DATA2
RETLW DATA3
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW
MOVLW
LOW constants
MOVWF
FSR1L
MOVLW
HIGH constants
MOVWF
FSR1H
MOVIW 0[FSR1]
;THE PROGRAM MEMORY IS IN W
Addresses
BANKx
x00h or x80h
INDF0
x01h or x81h
INDF1
x02h or x82h
PCL
x03h or x83h
STATUS
x04h or x84h
FSR0L
x05h or x85h
FSR0H
x06h or x86h
FSR1L
x07h or x87h
FSR1H
x08h or x88h
BSR
x09h or x89h
WREG
x0Ah or x8Ah
PCLATH
x0Bh or x8Bh
INTCON