Microchip Technology DM164130-7 Data Sheet
PIC16(L)F1946/47
DS41414D-page 314
2010-2012 Microchip Technology Inc.
25.4.1
AUTO-BAUD DETECT
The EUSART module supports automatic detection
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RXx signal, the RXx signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Setting the ABDEN bit of the BAUDxCON register
starts the auto-baud calibration sequence
(
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RXx signal, the RXx signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Setting the ABDEN bit of the BAUDxCON register
starts the auto-baud calibration sequence
(
). While the ABD sequence takes place,
the EUSART state machine is held in Idle. On the first
rising edge of the receive line, after the Start bit, the
SPxBRGL begins counting up using the BRG counter
clock as shown in
rising edge of the receive line, after the Start bit, the
SPxBRGL begins counting up using the BRG counter
clock as shown in
. The fifth rising edge will
occur on the RXx/DTx pin at the end of the eighth bit
period. At that time, an accumulated value totaling the
proper BRG period is left in the SPxBRGH:SPxBRGL
register pair, the ABDEN bit is automatically cleared,
and the RCxIF interrupt flag is set. A read operation on
the RCxREG needs to be performed to clear the RCxIF
interrupt. RCxREG content should be discarded. When
calibrating for modes that do not use the SPxBRGH
register the user can verify that the SPxBRGL register
did not overflow by checking for 00h in the SPxBRGH
register.
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in
period. At that time, an accumulated value totaling the
proper BRG period is left in the SPxBRGH:SPxBRGL
register pair, the ABDEN bit is automatically cleared,
and the RCxIF interrupt flag is set. A read operation on
the RCxREG needs to be performed to clear the RCxIF
interrupt. RCxREG content should be discarded. When
calibrating for modes that do not use the SPxBRGH
register the user can verify that the SPxBRGL register
did not overflow by checking for 00h in the SPxBRGH
register.
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in
. During ABD,
both the SPxBRGH and SPxBRGL registers are used
as a 16-bit counter, independent of the BRG16 bit set-
ting. While calibrating the baud rate period, the
SPxBRGH and SPxBRGL registers are clocked at
as a 16-bit counter, independent of the BRG16 bit set-
ting. While calibrating the baud rate period, the
SPxBRGH and SPxBRGL registers are clocked at
1/8th the BRG base clock rate. The resulting byte mea-
surement is the average bit time when clocked at full
speed.
surement is the average bit time when clocked at full
speed.
FIGURE 25-6:
AUTOMATIC BAUD RATE CALIBRATION
Note 1:
If the WUE bit is set with the ABDEN bit,
auto-baud detection will occur on the byte
following the Break character (see
auto-baud detection will occur on the byte
following the Break character (see
2:
It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
3:
During the auto-baud process, the
auto-baud counter starts counting at 1.
Upon completion of the auto-baud
sequence, to achieve maximum accu-
racy, subtract 1 from the SPxBRGH:SPx-
BRGL register pair.
auto-baud counter starts counting at 1.
Upon completion of the auto-baud
sequence, to achieve maximum accu-
racy, subtract 1 from the SPxBRGH:SPx-
BRGL register pair.
TABLE 25-6:
BRG COUNTER CLOCK
RATES
RATES
BRG16
BRGH
BRG Base
Clock
BRG ABD
Clock
0
0
F
OSC
/64
F
OSC
/512
0
1
F
OSC
/16
F
OSC
/128
1
0
F
OSC
/16
F
OSC
/128
1
1
F
OSC
/4
F
OSC
/32
Note:
During the ABD sequence, SPxBRGL and
SPxBRGH registers are both used as a
16-bit counter, independent of BRG16
setting.
SPxBRGH registers are both used as a
16-bit counter, independent of BRG16
setting.
BRG Value
RXx/DTx pin
ABDEN bit
RCxIF bit
bit 0
bit 1
(Interrupt)
Read
RCxREG
BRG Clock
Start
Auto Cleared
Set by User
XXXXh
0000h
Edge #1
bit 2
bit 3
Edge #2
bit 4
bit 5
Edge #3
bit 6
bit 7
Edge #4
Stop bit
Edge #5
001Ch
Note 1:
The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
SPxBRGL
XXh
1Ch
SPxBRGH
XXh
00h
RCIDL