Microchip Technology DM164130-7 Data Sheet
PIC16(L)F1946/1947
DS41414D-page 56
2010-2012 Microchip Technology Inc.
4.2
Register Definitions: Configuration Words
REGISTER 4-1:
CONFIG1: CONFIGURATION WORD 1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
FCMEN
IESO
CLKOUTEN
BOREN<1:0>
CPD
bit 13
bit 8
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
CP
MCLRE
PWRTE
WDTE<1:0>
FOSC<2:0>
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
-n = Value when blank or after Bulk Erase
bit 13
FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 12
IESO: Internal External Switchover bit
1 = Internal/External Switchover mode is enabled
0 = Internal/External Switchover mode is disabled
1 = Internal/External Switchover mode is enabled
0 = Internal/External Switchover mode is disabled
bit 11
CLKOUTEN: Clock Out Enable bit
If FOSC configuration bits are set to LP, XT, HS modes:
If FOSC configuration bits are set to LP, XT, HS modes:
This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin.
All other FOSC modes:
1 = CLKOUT function is disabled. I/O function on the CLKOUT pin.
0 = CLKOUT function is enabled on the CLKOUT pin
0 = CLKOUT function is enabled on the CLKOUT pin
bit 10-9
BOREN<1:0>: Brown-out Reset Enable bits
(1)
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the BORCON register
00 = BOR disabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the BORCON register
00 = BOR disabled
bit 8
CPD: Data Code Protection bit
(2)
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
0 = Data memory code protection is enabled
bit 7
CP: Code Protection bit
(3)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
0 = Program memory code protection is enabled
bit 6
MCLRE: MCLR/V
PP
Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1 = MCLR/V
PP
pin function is MCLR; Weak pull-up enabled.
0 = MCLR/V
PP
pin function is digital input; MCLR internally disabled; Weak pull-up under control of
WPUG5 bit.
bit 5
PWRTE: Power-up Timer Enable bit
(1)
1 = PWRT disabled
0 = PWRT enabled
0 = PWRT enabled
Note 1:
Enabling Brown-out Reset does not automatically enable Power-up Timer.
2:
The entire data EEPROM will be erased when the code protection is turned off during
3:
The entire program memory will be erased when the code protection is turned off.