Microchip Technology AC244045 Data Sheet
2010-2012 Microchip Technology Inc.
DS41440C-page 111
PIC16(L)F1825/1829
After the “BSF EECON1,WR” instruction, the processor
requires two cycles to set up the write operation. The
user must place two NOP instructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms, only during the cycle in which the write
takes place (i.e., the last word of the block write). This
is not Sleep mode as the clocks and peripherals will
requires two cycles to set up the write operation. The
user must place two NOP instructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms, only during the cycle in which the write
takes place (i.e., the last word of the block write). This
is not Sleep mode as the clocks and peripherals will
continue to run. The processor does not stall when
LWLO = 1, loading the write latches. After the write
cycle, the processor will resume operation with the third
instruction after the EECON1 write instruction.
LWLO = 1, loading the write latches. After the write
cycle, the processor will resume operation with the third
instruction after the EECON1 write instruction.
FIGURE 11-2:
BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES
14
14
14
14
Program Memory
Buffer Register
EEADRL<4:0> = 00000
Buffer Register
EEADRL<4:0> = 00001
Buffer Register
EEADRL<4:0> = 00010
Buffer Register
EEADRL<4:0> = 11111
EEDATA
EEDATH
7
5
0 7
0
6
8
First word of block
to be written
to be written
Last word of block
to be written