Microchip Technology AC244045 Data Sheet
PIC16(L)F1825/1829
DS41440C-page 176
2010-2012 Microchip Technology Inc.
19.2
Comparator Control
) contain
Control and Status bits for the following:
• Enable
• Output selection
• Output polarity
• Speed/Power selection
• Hysteresis enable
• Output synchronization
The CMxCON1 registers (see
• Enable
• Output selection
• Output polarity
• Speed/Power selection
• Hysteresis enable
• Output synchronization
The CMxCON1 registers (see
) contain
Control bits for the following:
• Interrupt enable
• Interrupt edge polarity
• Positive input channel selection
• Negative input channel selection
• Interrupt enable
• Interrupt edge polarity
• Positive input channel selection
• Negative input channel selection
19.2.1
COMPARATOR ENABLE
Setting the CxON bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
19.2.2
COMPARATOR OUTPUT
SELECTION
SELECTION
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CMOUT register. In order to
make the output available for an external connection,
the following conditions must be true:
• CxOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CMOUT register. In order to
make the output available for an external connection,
the following conditions must be true:
• CxOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set
19.2.3
COMPARATOR OUTPUT POLARITY
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a non-inverted output.
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a non-inverted output.
shows the output state versus input
conditions, including polarity control.
19.2.4
COMPARATOR SPEED/POWER
SELECTION
SELECTION
The trade-off between speed or power can be
optimized during program execution with the CxSP
control bit. The default state for this bit is ‘1’ which
selects the Normal Speed mode. Device power
consumption can be optimized at the cost of slower
comparator propagation delay by clearing the CxSP bit
to ‘0’.
optimized during program execution with the CxSP
control bit. The default state for this bit is ‘1’ which
selects the Normal Speed mode. Device power
consumption can be optimized at the cost of slower
comparator propagation delay by clearing the CxSP bit
to ‘0’.
19.3
Comparator Hysteresis
A selectable amount of separation voltage can be
added to the input pins of each comparator to provide a
hysteresis function to the overall operation. Hysteresis
is enabled by setting the CxHYS bit of the CMxCON0
register.
See
added to the input pins of each comparator to provide a
hysteresis function to the overall operation. Hysteresis
is enabled by setting the CxHYS bit of the CMxCON0
register.
See
for
more information.
Note 1:
The CxOE bit of the CMxCON0 register
overrides the PORT data latch. Setting
the CxON bit of the CMxCON0 register
has no impact on the port override.
overrides the PORT data latch. Setting
the CxON bit of the CMxCON0 register
has no impact on the port override.
2:
The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
TABLE 19-1:
COMPARATOR OUTPUT
STATE VS. INPUT
CONDITIONS
STATE VS. INPUT
CONDITIONS
Input Condition
CxPOL
CxOUT
CxV
N
> CxV
P
0
0
CxV
N
< CxV
P
0
1
CxV
N
> CxV
P
1
1
CxV
N
< CxV
P
1
0