Microchip Technology AC244045 Data Sheet
2010-2012 Microchip Technology Inc.
DS41440C-page 185
PIC16(L)F1825/1829
20.2
Option and Timer0 Control Register
TABLE 20-1:
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
REGISTER 20-1:
OPTION_REG: OPTION REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
WPUEN: Weak Pull-up Enable bit
1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUx latch values
1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUx latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5
TMR0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (F
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (F
OSC
/4)
bit 4
TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS<2:0>: Prescaler Rate Select bits
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CPSCON0
CPSON
CPSRM
—
—
CPSRNG<1:0>
CPSOUT
T0xCS
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
ADFVR<1:0>
INLVLA
—
—
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
OPTION_REG
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PS<2:0>
TMR0
Timer0 Module Register
*
TRISA
—
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
Legend:
— Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.
* Page provides register information.
000
001
010
011
100
101
110
111
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Bit Value
Timer0 Rate