Microchip Technology AC244045 Data Sheet
PIC16(L)F1825/1829
DS41440C-page 20
2010-2012 Microchip Technology Inc.
FIGURE 2-1:
CORE BLOCK DIAGRAM
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr 7
12
Addr MUX
FSR reg
STATUS reg
MUX
ALU
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
V
DD
8
8
Brown-out
Reset
12
3
V
SS
Configuration
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr 7
Addr MUX
FSR reg
STATUS reg
MUX
ALU
W Reg
Instruction
Decode &
Control
Timing
Generation
V
DD
8
8
3
V
SS
Configuration
15
Data Bus
8
14
Program
Bus
Instruction Reg
Program Counter
16-Level Stack
(15-bit)
Direct Addr 7
RAM Addr
Addr MUX
Indirect
Addr
FSR0 Reg
STATUS Reg
MUX
ALU
Instruction
Decode and
Control
Timing
Generation
V
DD
8
8
3
V
SS
Internal
Oscillator
Block
Configuration
Flash
Program
Memory
RAM
FSR reg
FSR reg
FSR1 Reg
15
15
MUX
15
Program Memory
Read (PMR)
12
FSR reg
FSR reg
BSR Reg
5