Microchip Technology AC244045 Data Sheet
2010-2012 Microchip Technology Inc.
DS41440C-page 217
PIC16(L)F1825/1829
24.2.5
COMPARE DURING SLEEP
The Compare mode is dependent upon the system
clock (F
clock (F
OSC
) for proper operation. Since F
OSC
is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
function properly during Sleep.
24.2.6
ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
registers, APFCON0 and APFCON1. To determine
which pins can be moved and what their default
locations are upon a Reset, see
other locations with the use of the alternate pin function
registers, APFCON0 and APFCON1. To determine
which pins can be moved and what their default
locations are upon a Reset, see
for more information.
TABLE 24-4:
SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
APFCON1
—
—
SDO2SEL
(2)
SS2SEL
(2)
P1DSEL
P1CSEL
P2BSEL
CCP2SEL
CCP1CON
P1M<1:0>
(1)
DC1B<1:0>
CCP1M<3:0>
CCP2CON
P2M<1:0>
(1)
DC2B<1:0>
CCP2M<3:0>
CCP3CON
—
—
DC3B<1:0>
CCP3M<3:0>
CCP4CON
—
—
DC4B<1:0>
CCP4M<3:0>
CCPRxL
Capture/Compare/PWM Register x Low Byte (LSB)
CCPRxH
Capture/Compare/PWM Register x High Byte (MSB)
INLVLA
—
—
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
INLVLC
INLVLC7
(2)
INLVLC6
(2)
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
INTCON
GIE PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
PIE2
OSFIE
C2IE
C1IE
EEIE
BCL1IE
—
—
CCP2IE
PIE3
—
—
CCP4IE
CCP3IE
TMR6IE
—
TMR4IE
—
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
PIR2
OSFIF
C2IF
C1IF
EEIF
BCL1IF
—
—
CCP2IF
PIR3
—
—
CCP4IF
CCP3IF
TMR6IF
—
TMR4IF
—
T1CON
TMR1CS<1:0>
T1CKPS<1:0>
T1OSCEN
T1SYNC
—
TMR1ON
T1GCON
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/DONE
T1GVAL
T1GSS<1:0>
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TRISA
—
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
TRISC
TRISC7
(2)
TRISC6
(2)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
Legend:
— Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode.
* Page provides register information.
Note
1:
Applies to ECCP modules only.
2:
PIC16(L)F1829 only.
3:
PIC16(L)F1825 only.